4.7.2. MCR, MCR2, MCRR

Move to coprocessor from ARM registers. Depending on the coprocessor, you might be able to specify various operations in addition.

Syntax

MCR{cond} coproc, opcode1, Rd, CRn, CRm{, opcode2}
MCR2 coproc, opcode1, Rd, CRn, CRm{, opcode2}
MCRR{cond} coproc, opcode1, Rd, Rn, CRm

where:

cond

is an optional condition code (see Conditional execution).

coproc

is the name of the coprocessor the instruction isfor. The standard name is pn, where n is an integer in the range 0-15.

opcode1

is a coprocessor-specific opcode.

Rd, Rn

are ARM source registers. They must not be r15.

CRn, CRm

are coprocessor registers.

opcode2

is an optional coprocessor-specific opcode.

Usage

The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.

Note

MCR2 is always unconditional.

Architectures

MCR is available in ARM architecture versions 2 and above.

MCR2 is available in ARM architecture versions 5 and above.

MCRR is available in E variants of ARM architecture v5 and above, excluding xP variants.

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