4.6.3. BLX

Branch with Link, and optionally exchange instruction set. This instruction has two alternative forms:


BLX{cond} Rm
BLX label



is an optional condition code (see Conditional execution).


is an ARM register containing the address to branchto.

Bit 0 of Rm is not used as part of the address.

If bit 0 of Rm is set, the instruction sets the T flag in the CPSR, and the code at the destination is interpreted as Thumb code.

If bit 0 of Rm is clear, bit 1 must not be set.


is a program-relative expression. See Register-relative and program-relative expressions for more information.


BLX label cannot be conditional. BLX label always causes a change to Thumb state.


The BLX instruction:

  • copies the address of the next instruction into r14 (lr, the link register)

  • causes a branch to label, or to the address held in Rm

  • changes instruction set to Thumb if either:

    • bit 0 of Rm is set

    • the BLX label form is used.

The machine-level BLX label instruction cannot branch to an address outside ±32Mb of the current instruction. When necessary, the ARM linker adds code to allow longer branches (see The ARM linker chapter in ADS Linker and Utilities Guide). The added code is called a veneer.


This instruction is available in all T variants of ARM architecture v5 and above.


    BLX     r2
    BLXNE   r0
    BLX     thumbsub

Incorrect example

    BLXMI   thumbsub    ; BLX label cannot be conditional
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