4.5.1. QADD, QSUB, QDADD, and QDSUB

Saturating Add, Saturating Subtract, Saturating Double and Add, Saturating Double and Subtract.

Syntax

op{cond} Rd, Rm, Rn

where:

op

is one of QADD, QSUB, QDADD,or QDSUB.

cond

is an optional condition code (see Conditional execution).

Rd

is the ARM register for the result.

Rm, Rn

are the ARM registers holding the operands.

r15 cannot be used for any of Rd, Rm, or Rn.

Usage

The QADD instruction adds the values in Rm and Rn.

The QSUB instruction subtracts the value in Rn from the value in Rm.

The QDADD instruction calculates SAT(Rm + SAT(Rn * 2)). Saturation can occur on the doubling operation, on the addition, or on both. If saturation occurs on the doubling but not on the addition, the Q flag is set but the final result is unsaturated.

The QDSUB instruction calculates SAT(Rm - SAT(Rn * 2)). Saturation can occur on the doubling operation, on the subtraction, or on both. If saturation occurs on the doubling but not on the subtraction, the Q flag is set but the final result is unsaturated.

Note

All values are treated as two’s complement signed integers by these instructions.

Condition flags

These instructions do not affect the N, Z, C, and V flags. If saturation occurs, they set the Q flag. To read the state of the Q flag, use an MRS instruction (see MRS).

Note

These instructions never clear the Q flag, even if saturation does not occur. To clear the Q flag, use an MSR instruction (see MSR).

Architectures

These instructions are available in E variants of ARM architecture v5 and above.

Examples

    QADD    r0,r1,r9
    QDSUBLT r9,r0,r1

Examples

    QSUBS   r3,r4,r2    ; use of S suffix not allowed
    QDADD   r11,r15,r0  ; use of r15 not allowed
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