4.2.2. LDR and STR, halfwords and signed bytes

Load register, signed 8-bit bytes and signed and unsigned 16-bit halfwords.

Store register, 16-bit halfwords.

Signed loads are sign-extended to 32 bits. Unsigned halfword loads are zero-extended to 32 bits.


These instructions have four possible forms:

  • zero offset

  • pre-indexed offset

  • program-relative

  • post-indexed offset.

The syntax of the four forms, in the same order, are:

op{cond}	type Rd, [Rn]
op{cond}	type Rd, [Rn, Offset]{!}
op{cond}	type Rd, label
op{cond}	type Rd, [Rn], Offset



is either LDR or STR.


is an optional condition code (see Conditional execution).


must be one of:


for Signed Halfword (LDR only)


for unsigned Halfword


for Signed Byte (LDR only).


is the ARM register to load or save.


is the register on which the memory address is based.

Rn must not be the sameas Rd, if the instruction is either:

  • pre-indexed with writeback

  • post-indexed.


is a program-relative expression. See Register-relative and program-relative expressions for more information. label must be within ±255 bytes of the current instruction.


is an offset applied to the value in Rn (see Offset syntax).


is an optional suffix. If ! is present, the address including the offset is written back into Rn. You cannot use the ! suffix if Rn is r15.

Zero offset

The value in Rn is used as the address for the transfer.

Pre-indexed offset

The offset is applied to the value in Rn before the transfer takes place. The result is used as the memory address for the transfer. If the ! suffix is used, the result is written back into Rn.


This is an alternative version of the pre-indexed form. The assembler calculates the offset from the PC for you, and generates a pre-indexed instruction with the PC as Rn.

You cannot use the ! suffix.

Post-indexed offset

The value in Rn is used as the memory address for the transfer. The offset is applied to the value in Rn after the transfer takes place. The result is written back into Rn.

Offset syntax

Both pre-indexed and post-indexed offsets can be either of the following:




is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset is added to Rn.


is an expression evaluating to an integer in the range –255 to +255. This is often a numeric constant (see examples below).


is a register containing a value to be used as the offset.

The offset syntax is the same for LDR and STR, doublewords.

Address alignment for halfword transfers

The address must be even for halfword transfers.

If your system has a system coprocessor (cp15), you can enable alignment checking. Non halfword-aligned 16-bit transfers cause an alignment exception if alignment checking is enabled.

If your system does not have a system coprocessor (cp15), or alignment checking is disabled:

  • a non halfword-aligned 16-bit load corrupts Rd

  • a non halfword-aligned 16-bit save corrupts two bytes at [address] and [address–1].

Loading to r15

You cannot load halfwords or bytes to r15.


These instructions are available in ARM architecture v4 and above.


    LDREQSH r11,[r6]        ; (conditionally) loads r11 with a 16-bit halfword
                            ; from the address in r6. Sign extends to 32 bits.
    LDRH    r1,[r0,#22]     ; load r1 with a 16 bit halfword from 22 bytes
                            ; above the address in r0. Zero extend to 32 bits.
    STRH    r4,[r0,r1]!     ; store the least significant halfword from r4
                            ; to two bytes at an address equal to contents(r0)
                            ; plus contents(r1). Write address back into r0.
    LDRSB   r6,constf       ; load a byte located at label constf. Sign extend.

Incorrect example

    LDRSB   r1,[r6],r3,LSL#4    ; This format is only available for word and
                                ; unsigned byte transfers.
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