4.1. Conditional execution

Almost all ARM instructions can include an optional condition code. This is shown in syntax descriptions as {cond}. An instruction with a condition code is only executed if the condition code flags in the CPSR meet the specified condition. The condition codes that you can use are shown in Table 4.2.

Table 4.2. ARM condition codes

EQZ setEqual
NEZ clearNot equal
CS/HS C set Higher or same (unsigned >= )
CC/LOC clearLower (unsigned < )
MIN setNegative
PLN clearPositive or zero
VSV setOverflow
VCV clearNo overflow
HIC set and Z clearHigher (unsigned <= )
LSC clear or Z setLower or same (unsigned <= )
GEN and V the sameSigned >=
LTN and V differentSigned <
GTZ clear, and N and V the sameSigned >
LEZ set, or N and V differentSigned <=
ALAnyAlways (usually omitted)

Almost all ARM data processing instructions can optionally update the condition code flags according to the result. To make an instruction update the flags, include the S suffix as shown in the syntax description for the instruction.

Some instructions (CMP, CMN, TST and TEQ) do not require the S suffix. Their only function is to update the flags. They always update the flags.

Flags are preserved until updated. A conditional instruction which is not executed has no effect on the flags.

Some instructions update a subset of the flags. The other flags are unchanged by these instructions. Details are specified in the descriptions of the instructions.

You can execute an instruction conditionally, based upon the flags set in another instruction, either:

For further information, see Conditional execution.

Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DUI 0068B