4.2.3. LDR and STR, doublewords

Load two consecutive registers and store two consecutive registers, 64-bit doubleword.


These instructions have four possible forms:

  • zero offset

  • pre-indexed offset

  • program-relative

  • post-indexed offset.

The syntax of the four forms are, in the same order:

op{cond}D Rd, [Rn]
op{cond}D Rd, [Rn, Offset]{!}
op{cond}D Rd, label
op{cond}D Rd, [Rn], Offset



is either LDR or STR.


is an optional condition code (see Conditional execution).


is one of the ARM registers to load or save. Theother one is R(d+1). Rd must be an even numbered register, and not r14.


is the register on which the memory address is based.

Rn must not be the same as Rd or R(d+1), unless the instruction is either:

  • zero offset

  • pre-indexed without writeback.


is an offset applied to the value in Rn (see Offset syntax).


is a program-relative expression. See Register-relative and program-relative expressions for more information.

label must be within ±252 bytes of the current instruction.


is an optional suffix. If ! is present, the final address including the offset is written back into Rn.

Zero offset

The value in Rn is used as the address for the transfer.

Pre-indexed offset

The offset is applied to the value in Rn before the transfers take place. The result is used as the memory address for the transfers. If the ! suffix is used, the address is written back into Rn.


This is an alternative version of the pre-indexed form. The assembler calculates the offset from the PC for you, and generates a pre-indexed instruction with the PC as Rn.

You cannot use the ! suffix.

Post-indexed offset

The value in Rn is used as the memory address for the transfer. The offset is applied to the value in Rn after the transfer takes place. The result is written back into Rn.

Offset syntax

Both pre-indexed and post-indexed offsets can be either of the following:




is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset is added to Rn.


is an expression evaluating to an integer in the range –255 to +255. This is often a numeric constant (see examples below).


is a register containing a value to be used as the offset. For loads, Rm must not be the same as Rd or R(d+1).

This is the same offset syntax as for LDR and STR, halfwords and signed bytes.

Address alignment

The address must be a multiple of eight for doubleword transfers.

If your system has a system coprocessor, you can enable alignment checking. Non doubleword-aligned 64-bit transfers cause an alignment exception if alignment checking is enabled.


These instructions are available in E variants of ARM architecture v5 and above.


    LDRD    r6,[r11]
    LDRMID  r4,[r7],r2
    STRD    r4,[r9,#24]
    STRD    r0,[r9,-r2]!
    LDREQD  r8,abc4

Incorrect examples

    LDRD    r1,[r6]        ; Rd must be even.
    STRD    r14,[r9,#36]   ; Rd must not be r14.
    STRD    r2,[r3],r6     ; Rn must not be Rd or R(d+1).
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