6.7.13. FMRRS and FMSRR

Transfer contents between two single-precision floating-point registers and two ARM registers.

Syntax

FMRRS{cond} Rd, Rn, {Sn,Sm}
FMSRR{cond} {Sn,Sm}, Rd, Rn

where:

cond

is an optional condition code (see VFP and condition codes).

Sn, Sm

are two consecutive VFP single-precision registers.

Rd, Rn

are the ARM registers. Do not use r15.

Usage

The FMRRS instruction transfersthe contents of Sn into Rd, and the contents of Sm into Rn.

The FMSRR instruction transfers the contents of Rd into Sn, and the contents of Rn into Sm.

Exceptions

These instructions do not produce any exceptions.

Architectures

These instructions are available in VFPv2 and above.

Examples

    FMRRS       r2, r3, {s0,s1}
    FMSRRNE     {s27,s28}, r5, r2

Incorrect examples

    FMRRS       r2, r3, {s2,s4}     ; VFP registers must be consecutive
    FMSRR       {s5,s6}, r15, r0    ; you must not use r15
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