4.2.5. PLD

Cache preload.

Syntax

PLD [Rn{, FlexOffset}]

where:

Rn

is the register on which the memory address is based.

FlexOffset

is an optional flexible offset applied to the valuein Rn.

FlexOffset can be either of the following:


#expr


{-}Rm{, shift}

where:

-

is an optional minus sign. If - is present, the offset is subtracted from Rn. Otherwise, the offset is added to Rn.

expr

is an expression evaluating to an integer in the range –4095 to +4095. This is often a numeric constant.

Rm

is a register containing a value to be used as the offset.

shift

is an optional shift to be applied to Rm. It can be any one of:

ASR n

arithmetic shift right n bits. 1 = n = 32.

LSL n

logical shift left n bits. 0 = n = 31.

LSR n

logical shift right n bits. 1 = n = 32.

ROR n

rotate right n bits. 1 = n = 31.

RRX

rotate right one bit, with extend.

This is the same offset syntax as for LDR and STR, words and unsigned bytes.

Usage

Use PLD to hint to the memory system that there is likely to be a load from the specified address within the next few instructions. The memory system can use this to speed up later memory accesses.

Alignment

There are no alignment restrictions on the address. If a system control coprocessor (cp15) is present then it will not generate an alignment exception for any PLD instruction.

Architectures

This instruction is available in E variants of ARM architecture v5 and above.

Examples

    PLD [r2]
    PLD [r15,#280]
    PLD [r9,#-2481]
    PLD [r0,#av*4]  ; av * 4 must evaluate, at assembly time, to
                    ; an integer in the range -4095 to +4095
    PLD [r0,r2]
    PLD [r5,r8,LSL 2]
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