2.3.4. An example Thumb assembly language module

Example 2.3 illustrates some of the core constituents of a Thumb assembly language module. It is based on subrout.s. It is supplied as thumbsub.s in the examples\asm subdirectory of the ADS. Refer to Code examples for instructions on how to assemble, link, and execute the example.

Example 2.3. 

        AREA ThumbSub, CODE, READONLY   ; Name this block of code
        ENTRY                           ; Mark first instruction to execute
        CODE32                          ; Subsequent instructions are ARM
header  ADR     r0, start + 1           ; Processor starts in ARM state,
        BX      r0                      ; so small ARM code header used
                                        ; to call Thumb main program
        CODE16                          ; Subsequent instructions are Thumb
        MOV     r0, #10                 ; Set up parameters
        MOV     r1, #3
        BL      doadd                   ; Call subroutine
        MOV     r0, #0x18               ; angel_SWIreason_ReportException
        LDR     r1, =0x20026            ; ADP_Stopped_ApplicationExit
        SWI     0xAB                    ; Thumb semihosting SWI
        ADD     r0, r0, r1              ; Subroutine code
        MOV     pc, lr                  ; Return from subroutine
        END                             ; Mark end of file

CODE32 and CODE16 directives

These directives instruct the assembler to assemble subsequent instructions as ARM (CODE32) or Thumb (CODE16) instructions. They do not assemble to an instruction to change the processor state at runtime. They only change the assembler state.

The ARM assembler, armasm, starts in ARM mode by default. You can use the -16 option in the command line if you want it to start in Thumb mode.

BX instruction

This instruction is a branch that can change processor state at runtime. The least significant bit of the target address specifies whether it is an ARM instruction (clear) or a Thumb instruction (set). In this example, this bit is set in the ADR pseudo-instruction.

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