A.1. AHB VHDL files

Table A.1 shows VHDL file dependencies for the AHB.

Table A.1. AHB VHDL file dependencies

Library

File

Type

Dependencies

apb_easy

FRC.vhd

Entity/architecture

ieee.std_logic_1164

ieee.std_logic_unsigned."-"

IntCntl.vhd

Entity/architecture

ieee.std_logic_1164

MuxP2B.vhd

Entity/architecture

ieee.std_logic_1164

RemPause.vhd

Entity/architecture

ieee.std_logic_1164

RPS.vhd

Entity/architecture

ieee.std_logic_1164

apb_easy.IntCntl

apb_easy.MuxP2B

apb_easy.RemPause

apb_easy.Timers

Timers.vhd

Entity/architecture

ieee.std_logic_1164

ieee.std_logic_unsigned."-"

apb_easy.FRC

ahb_easy

APBif.vhd

Entity/architecture

ieee.std_logic_1164

Arbiter.vhd

Entity/architecture

ieee.std_logic_1164

ieee.std_logic_unsigned."-"

Decoder.vhd

Entity/architecture

ieee.std_logic_1164

DefaultSlave.vhd

Entity/architecture

ieee.std_logic_1164

EASY.vhd

Entity/architecture

ieee.std_logic_1164

apb_easy.RPS

ahb_easy.APBif

ahb_easy.Arbiter

ahb_easy.Decoder

ahb_easy.DefaultSlave

ahb_easy.MuxS2M

ahb_easy.MuxM2S

ahb_easy.ResCntl

ahb_easy.RetrySlave

ahb_easy.SMI

ahb_easy.TIC

behavioural.IntMem

core.A7TDMI

MuxM2S.vhd

Entity/architecture

ieee.std_logic_1164

MuxS2M.vhd

Entity/architecture

ieee.std_logic_1164

ResCntl.vhd

Entity/architecture

ieee.std_logic_1164

RetrySlave.vhd

Entity/architecture

ieee.std_logic_1164,

ieee.std_logic_unsigned."-"

SMI.vhd

Entity/architecture

ieee.std_logic_1164,

ieee.std_logic_unsigned."-"

TIC.vhd

Entity/architecture

ieee.std_logic_1164

ieee.std_logic_unsigned."+"

behavioural

ExtRAM.vhd

Entity/architecture

ieee.std_logic_1164

std.textio

common.Conv

ExtROM.vhd

Entity/architecture

ieee.std_logic_1164

std.textio

common.Conv

IntMem.vhd

Entity/architecture

ieee.std_logic_1164

std.textio

common.Conv

Memory.vhd

Entity/architecture

ieee.std_logic_1164

behavioural.ExtRAM

behavioural.ExtROM

Ticbox.vhd

Entity/architecture

ieee.std_logic_1164

std.textio

common.Conv

Tube.vhd

Entity/architecture

ieee.std_logic_1164

std.textio

common.Conv

common

Conv.vhd

Package

ieee.std_logic_1164

core

A7TWrap.vhd

Entity/architecture

ieee.std_logic_1164

core.A7TWrapBurst

core.A7TWrapCtrl

core.A7TWrapLock

core.A7TWrapMaster

core.A7TWrapTest

A7TWrapBurst.vhd

Entity/architecture

ieee.std_logic_1164

ieee.std_logic_unsigned."+"

A7TWrapCtrl.vhd

Entity/architecture

ieee.std_logic_1164

A7TWrapLock.vhd

Entity/architecture

ieee.std_logic_1164

A7TWrapMaster.vhd

Entity/architecture

ieee.std_logic_1164

A7TWrapTest.vhd

Entity/architecture

ieee.std_logic_1164

A7TDMI.vhd

Entity/architecture

ieee.std_logic_1164

core.A7TWrap

Core simulation model library

tbench

TBEasy.vhd

Entity/architecture

ieee.std_logic_1164

ahb_easy.EASY

behavioural.Memory

behavioural.Tube

TBTic.vhd

Entity/architecture

ieee.std_logic_1164

ahb_easy.EASY

behavioural.Ticbox

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