Example AMBA™ SYstem User Guide 4.2.3. ASB synthesis scripts

4.2.3. ASB synthesis scripts

There are five main synthesis scripts that are used by each module in the ASB EASY system:

<module>.cmd: The synthesis command file contains the dc_shell command list used to synthesize the module.
<module>.scr: The synthesis constraints file contains the timing constraints for the module input and output ports that are not included in the standard .scr files.
apb_slave.scr, asb_master.scr, asb_slave.scr: These contain generic port timing information for the standard APB and ASB signals (such as BD, PRDATA) for APB peripherals, and ASB masters and slaves.
global.scr: The global file sets up the system clock parameters (default 40MHz = 25ns clock), ARM7TDMI wrapper output timings on the ASB signals, and sets the general system operating conditions.
setup.scr: The setup file configures the cell libraries used by the system (current default is q1cells), HDL to synthesize to (default is vhdl), and other standard dc_shell settings.

Additional shell scripts, namely the run_hdl_bus_module files found in the synopsys directory, exist to start the synthesis process. These scripts:

copy the chosen HDL source file from the ../hdl directory into the synthhdl directory
start dc_shell with the module.cmd synthesis script
pipe the output command log into the file log/module_hdl.log.

File conversion

Some VHDL source files use the conversion program hhd2synth to make them compatible for synthesis.

The conversion:

removes any after statements that are in the code
changes rising_edge to CLK’ event and CLK = 1 for compatibility with Synopsys versions previous to 1998.02
performs other processing as described in the synopsys/vhd2synth.txt file.

Note

The vhd2synth conversion program writes output files only with lowercase filenames. Because the <module>.cmd files supplied expect mixed-case VHDL filenames, the converted VHDL files must be renamed to their original mixed-case format. This renaming is done to the ARM7TDMI core wrapper files that require conversion only by the run_vhdl_A7Wrap script.

Run script files

There is a run_hdl_bus_module file for each synthesizable module of the standard EASY system.

The combined script run_hdl_asb_ALL:

calls the other run_hdl_bus_module scripts for the same hdl
creates the two extra log files named errors_hdl.txt and violated_hdl.txt.

The run_hdl_asb_ALL script generates the extra log files using grep to find the words Error and VIOLATED in the module_hdl.log files. Each of these words indicates a problem with the synthesis process. Violated_hdl.txt always contains at least one line for each module, due to using the command set_max_area 0, which always creates a VIOLATED message.

Synthesis results

Synthesizing the module creates the following files:

db/module_hdl.db
log/module_hdl.log
netlist/net_module.v(hd).

Housekeeping

Error and Violated log files are created only when all the modules are synthesized using the run_hdl_asb_ALL scripts. When you are synthesizing single modules, check for errors, warnings, and violations on the output log file.

When there are no errors or timing violations, you can simulate the netlist by copying the net_module.v(hd) file into the relevant ../hdl/ directory, assuming a simulation version of the cell library used for synthesis is available.

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