Example AMBA ™ SYstem UserGuide

Table of Contents

About this document
Intended audience
Typographical conventions
Further reading
ARM publications
Feedback on this document
Feedback on the Example AMBA SYstem
1. Introduction
1.1. ASB-based EASY systems
1.2. Structure of the EASY system
1.2.1. EASY system blocks
1.2.2. EASY components
1.2.3. AMBA bus master logic
1.2.4. Standard EASY component modifications
1.3. General system structure
1.3.1. The file structure
1.3.2. The system hierarchy
1.3.3. The system connection layout
2. Initialization
2.1. System setup
3. Simulation
3.1. Simulation setup
3.2. System compilation
3.3. TBTic test bench
3.3.1. Setting the TBTic clock frequency
3.3.2. Inputting data to the TBTic test bench
3.4. TBEasy test bench
3.4.1. External memory module
3.4.2. Setting the TBEasy clock frequency
3.4.3. Program message and simulation termination control
3.4.4. Inputting data to the TBEasy test bench
3.5. Simulation messages
3.5.1. Startup messages
3.5.2. ARM core messages
3.5.3. Buswatcher messages (ASB only)
3.5.4. TICTalk messages
3.5.5. Netlist messages
3.5.6. Other messages
3.6. Test programs
3.6.1. easy_c.c
3.6.2. easy_asm.s
3.7. Setup to simulate a synthesized EASYsystem
3.7.1. Setting up a cell library
3.7.2. Simulating the system files
4. ASB Synthesis
4.1. Synthesizing the EASY system
4.2. EASY synthesis process
4.2.1. Requirements for the default EASYsystem for synthesis
4.2.2. Purpose of synthesis scripts
4.2.3. ASB synthesis scripts
4.3. Synthesizing new ASB modules
5. AHB Synthesis
5.1. Synthesizing the EASY system
5.2. EASY synthesis process
5.2.1. Requirements for the default EASYsystem for synthesis
5.2.2. Purpose of synthesis scripts
5.2.3. System synthesis scripts
5.2.4. Synthesis timing constraints
5.2.5. Synthesis results
5.2.6. Using a different technology celllibrary
5.3. Synthesizing new AHB modules
A. HDL Libraries and Dependencies
A.1. AHB VHDL files
A.2. AHB Verilog file
A.3. ASB VHDL files
A.4. ASB Verilog files

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties or merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.


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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A October1998 First release
Revision B July1999 Include AHB
Revision C August1999 Include corrections and wrapper infomation
Copyright © 1998-1999. All rights reserved. ARM DUI 0092C