When TDT is used with an XScale target, the debug hardware and XScale core are embedded within an XScale Application Specific Standard Product (ASSP). Figure 7.1 shows the overall system and the interaction between the components when an XScale target is used. See Setting up the trace hardware for XScale for details on setting up your hardware.
The elements that provide the capability to trace instructions and/or data accesses in real time are:
- XScale core
This is a processor core based on the Intel® XScale™ Microarchitecture core. The XScale core cannot trace data, and only traces instructions.
- Debug hardware
The debug hardware performs debug functions such as setting breakpoints and watchpoints. It also maintains a control flow history, which is used by the TDT software to create an instruction trace. No external trace capture hardware is therefore required, but the buffer is relatively small.
- Trace Debug Tools
This retrieves the data from the debug hardware, and reconstructs a historical view of processor activity. See The Trace Debug Tools (TDT) for more details.
The JTAG interface is a protocol converter, such as Multi-ICE, that converts low-level commands (such as programming a register) from AXD into JTAG messages for the XScale debug logic.
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