B.2.2. Timing parameter tables
Table B.3 shows
the clock and reset timing parameters.
Table B.3. Clock and reset parameters
| Parameter | Description | Typ |
|---|
| Tclk | HCLK clock
period | 30 |
| Tisrst | HRESETn deasserted
setup time before HCLK | 15 |
Table B.4 shows
the AHB slave input parameters.
Table B.4. AHB slave input parameters
| Parameter | Description | Typ |
|---|
| Tistr | Transfer type setup time before HCLK | 5 |
| Tisa | HADDR[31:0] setup
time before HCLK | 10 |
| Tisctl | HWRITE, HSIZE[2:0] and HBURST[2:0] setup
time before HCLK | 5 |
| Tiswd | Write data setup time before HCLK | 5 |
| Tisrdy | Ready setup time before HCLK | 5 |
Table B.5 shows
the AHB slave output parameters.
Table B.5. AHB slave output parameters
| Parameter | Description | Typ |
|---|
| Tovrsp | Response valid time after HCLK | 15 |
| Tovrd | Data valid time after HCLK | 15 |
| Tovrdy | Ready valid time after HCLK | 15 |
Table B.6 shows
the bus master input parameters.
Table B.6. Bus master input timing parameters
| Parameter | Description | Typ |
|---|
| Tisgnt | HGRANTx setup
time before HCLK | 5 |
| Tisrdy | Ready setup time before HCLK | 5 |
| Tisrsp | Response setup time before HCLK | 5 |
| Tisrd | Read data setup time before HCLK | 5 |
Table B.7 shows
the bus master output timing parameters.
Table B.7. Bus master output timing parameters
| Parameter | Description | Typ |
|---|
| Tovtr | Transfer type valid time after HCLK | 15 |
| Tova | Address valid time after HCLK | 15 |
| Tovctl | HWRITE, HSIZE[2:0] and HBURST[2:0] valid
time after HCLK | 15 |
| Tovwd | Write data valid time after HCLK | 15 |
| Tovreq | Request valid time after HCLK | 15 |
| Tovlck | Lock valid time after HCLK | 15 |
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