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| Home > Features specific to the CM1136JF-S > ARM1136JF-S test chip characteristics |
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The CM1136JF-S Core Module uses test chips that conform to the generic test chip specification. The test chip in the CM1136JF-S contains:
a Clock Generator Control Block that configures the clocking scheme for the core
an AHB matrix
a vectored interrupt controller (VIC)
16KB of Data and 16KB of Instruction tightly-coupled memory (TCM)
16KB of Data and 16KB of Instruction cache
The test chip is contains an ETM11RV embedded trace macrocell. See the ETM11RV Technical Reference Manual for more details on the ETM.
See the ARM1136JF-S Technical Reference Manual for further details of the TCMs and cache memory.
The standard cache and TCM size is 16KB, but some core modules versions might have larger sized memories. Refer to the release notes supplied with your core module for details.
| Copyright © 2000-2005 ARM Limited. All rights reserved. | ARM DUI 0138E |
| Non-Confidential | |
| PDF version | |
| Home > Features specific to the CM1136JF-S > ARM1136JF-S test chip characteristics |