Integrator®/CM926EJ-S, CM946E-S, CM966E-S, CM1026EJ-S, and CM1136JF-S User Guide C.2.5. AHB address map

C.2.5. AHB address map

Table C.4 lists the base address of the various ARM1136JF-S test chip AHB peripherals. These peripherals are multiply mapped throughout their allocated address ranges. The table also indicates the ARM1136JF-S AHB-Lite ports that are able to access each peripheral.

Table C.4. Test chip address map

Module name	Address	Accessible from	Size	Description
TestChipRAM (BANK0)	`0x3FFFFFFF`- `0x3F800000`	Instruction read, Data Read, Data Write	4MB	Internal 64-bit primary test chip RAM bank. Interleaved on 1KB boundaries with BANK1. Actual size of this RAM depends on the space available within the test chip, but typically it is 256KB.
TestChipRAM (BANK1)	`0x3FFFFFFF`- `0x3F800000`	Instruction read, Data Read, Data Write	4MB	Internal 64-bit primary test chip RAM bank. Interleaved on 1KB boundaries with BANK0. Actual size of this RAM depends on the space available within the test chip, but typically it is 256KB.
SPARE	`0x3F7FFFFF`- `0x3F400000`	All ports	4MB	SPARE (access is presented on the test chip AHB interface).
Etb11TraceSRAM	`0x3F3FFFFF`- `0x3F380000`	All ports	512KB	ETB11 memory.
ETBREG	`0x3F37FFFF`- `0x3F300000`	All ports	512KB	ETB11 registers.
AHBPCAPT	`0x3F2FFFFF`- `0x3F200000`	All ports	1MB	Pin capture and ETM11RV validation control.
AHBVIC	`0x3F1FFFFF`- `0x3F100000`	All ports	1MB	Control port for VIC.
XRAM2Kx32	`0x3F0FFFFF`- `0x3F000000`	All ports	1MB	Secondary test chip RAM, 32-bit AHB RAM. 8KB RAM implemented within this space, otherwise wraps.

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