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| Home > Features specific to the CM1136JF-S > ARM1136JF-S test chip characteristics > Vectored Interrupt Controller (VIC) block |
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The VIC has the following interfaces:
interrupt sources
AHB slave interface to control the VIC
daisy chain interface to connect two or more VICs together
scan chain interface.
There are 32 interrupt source inputs. For details of the VIC interrupts sources connections, see the ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual.
The daisy chain interface is tied off, because only a single VIC is present in the ARM1136JF-S test chip. By default, the VIC is disabled. Use the Test Chip Control Register to enable the VIC (see Table C.12).
Table C.24 lists the ARM1136JF-S test chip signal routing to the VIC interrupt sources.
Table C.24. Test chip interrupt routing
| VIC input | Source | Comment |
|---|---|---|
| VICINTSOURCE[0] | NOT (nFIQ) | Pin on the test chip |
| VICINTSOURCE[1] | NOT (nVALFIQ) | ARM1136JF-S output |
| VICINTSOURCE[6] | COMMRX | ARM1136 JF-S output |
| VICINTSOURCE[7] | COMMTX | ARM1136 JF-S output |
| VICINTSOURCE[10] | NOT (nIRQ) | Pin on the test chip |
| VICINTSOURCE[11] | NOT (nVALIRQ) | ARM1136 JF-S output |
| VICINTSOURCE[12] | NOT (nDMAIRQ) | ARM1136 JF-S output |
| VICINTSOURCE[13] | NOT (nPMUIRQ) | ARM1136 JF-S output |
| VICINTSOURCE[14] | NOT (nVALRESET) | ARM1136 JF-S output |
All other VICINTSOURCE signals are tied to 0.
| Copyright © 2000-2005 ARM Limited. All rights reserved. | ARM DUI 0138E |
| Non-Confidential | |
| PDF version | |
| Home > Features specific to the CM1136JF-S > ARM1136JF-S test chip characteristics > Vectored Interrupt Controller (VIC) block |