The data routing for processor writes to the system bus is illustrated in Figure 5.5.

The data, address, and control information associated with the transfer are posted into a buffer, and the transfer on the system bus occurs some time later when that bus is available. System bus error responses to write transfers are reported back to the processor as Data Aborts.

For some other core modules, a full buffer results in the processor receives a wait response until space becomes available. The FIFO is only a buffer, so only the first access completes in one cycle.

The data routing for processor reads from the system bus is illustrated in Figure 5.6.

The order of processor transactions is preserved on the system bus. The processor receives a wait response until the read transfer has completed on the system bus, after that it receives the data and any associated bus error response from the system bus.