Processor reset

Output

The ARM_nPORESET signal is used to reset the processor core. It is generated from nSRST LOW when the core module is used standalone, or nSYSRST LOW when the core module is attached to a motherboard.

It is asserted as soon as the appropriate input becomes active. It is deasserted synchronously from the falling edge of the processor bus clock.

nMBDET

Motherboard detect

Input

The nMBDET signal is pulled LOW when the core module is attached to a motherboard and HIGH when the core module is used standalone.

When MBDET is LOW, nSYSRST is used to generate the ARM_nPORESET signal.

When nMBDET is HIGH, nSRST is used to generate the ARM_nPORESET signal.

PBRST

Push-button reset

Input

The PBRST signal is generated by pressing the reset button.

nSRST

System reset

Bidirectional

The nSRST open collector output signal is driven LOW by the core module FPGA when the signal PBRST or software reset (SWRST) is asserted.

As an input, nSRST can be driven LOW by Multi-ICE.

If there is no motherboard present, the nSRST signal is synchronized to the processor bus clock to generate the ARM_nPORESET signal.

nSYSRST

System reset

Input

The nSYSRST signal is generated by the system controller FPGA on the motherboard. It is used to generate the ARM_nPORESET signal when the core module is attached to a motherboard. It is selected by the motherboard detect signal (nMBDET).