Integrator ® /CM926EJ-S,CM946E-S, CM966E-S, CM1026EJ-S, and CM1136JF-S User Guide

HBI-0087: CM926EJ-S, CM1026EJ-S, and CM1136JF-S HBI-0066:CM946E-S and CM966E-S


Table of Contents

Preface
About this document
Intended audience
Organization
Typographical conventions
Further reading
Feedback
Feedback on this document
Feedback on the ARM Integrator coremodules
1. Introduction
1.1. About the core modules
1.2. Overview of the Integrator/CMx6
1.2.1. System architecture
1.2.2. ARM processor test chip
1.2.3. Core module FPGA
1.2.4. Volatile memory
1.2.5. Clock generation
1.2.6. Multi-ICE connector
1.2.7. Power supply control
1.2.8. CP peripherals
1.3. Links and indicators
1.3.1. CONFIG link
1.3.2. LED indicators
1.4. Test points
1.5. Precautions
1.5.1. Ensuring safety
1.5.2. Preventing damage
1.5.3. Ensuring correct operation
2. Getting Started
2.1. Setting up a standalone core module
2.1.1. Fitting an SDRAM DIMM
2.1.2. Using the core module without SDRAM
2.1.3. Connecting power
2.1.4. Connecting Multi-ICEor RealView ICE and Multi-Trace
2.2. Attaching the core module to an Integrator/APmotherboard
2.2.1. Core module ID
2.2.2. SDRAM, Trace, and Multi-ICE
2.2.3. Powering the assembled Integrator/AP development system
2.3. Attaching the core module to an Integrator/CPbaseboard
2.3.1. FPGA image
2.3.2. Core module ID
2.3.3. SDRAM, Trace, and Multi-ICE
2.3.4. Powering the assembled Integrator/CP development system
3. Hardware Description
3.1. ARM microprocessor test chip
3.1.1. Test chip overview
3.1.2. Test chip configuration control
3.1.3. Fixed value test chip configuration controls
3.2. Core module FPGA
3.2.1. Integrator/AP FPGA image
3.2.2. Integrator/CP FPGA image
3.2.3. FPGA image selection
3.3. Memory
3.3.1. SSRAM controller
3.3.2. SDRAM operating mode
3.3.3. Serial presence detect
3.4. Clock generators
3.4.1. Clock generation functionaloverview
3.4.2. Programming the clocks
3.4.3. Test chip clocks
3.5. Multi-ICE support
3.5.1. JTAG scan paths
3.5.2. JTAG connection modes
3.5.3. JTAG signals
3.5.4. Debug communicationsinterrupts
3.6. Embedded Trace support
3.6.1. About using trace
3.6.2. Core module trace configuration
3.6.3. Trace interface description
3.7. Stacking options
3.8. Power supply control (CM926EJ-S, CM1026EJ-S,and CM1136JF-S only)
3.8.1. Reading the voltages
3.8.2. Setting the VDDCORE voltage
4. Programmer’s Reference
4.1. About the memory map
4.1.1. TCM state after reset
4.1.2. TCM size and aliasing (CM946E-S and CM966E-S)
4.2. Core module memory map configuration
4.2.1. SSRAM mode selection(CM946E-S and CM966E-S only)
4.2.2. Using REMAP
4.3. SSRAM alias
4.4. SDRAM mapping
4.4.1. Local access
4.5. Processor configuration
4.5.1. Limitations
4.5.2. Identifying the test chip type on your core module
4.6. Core module control registers
4.6.1. Core module ID register
4.6.2. Core module processor register
4.6.3. Core module status register
4.6.4. Core module oscillator register
4.6.5. Core module control register
4.6.6. Core module lock register
4.6.7. Core module local memory bus cycle counter
4.6.8. Core module auxiliary oscillator register
4.6.9. SDRAM status and controlregister
4.6.10. Core module initializationregister
4.6.11. Core module reference clock cycle counter
4.7. Core module flag registers
4.7.1. Flag/nonvolatile flag register
4.7.2. Flag/nonvolatile flag set register
4.7.3. Flag/nonvolatile flag clear register
4.8. Core module interrupt registers
4.8.1. IRQ/FIQ status register
4.8.2. IRQ/FIQ raw status register
4.8.3. IRQ/FIQ enable set register
4.8.4. IRQ/FIQ enable clear register
4.8.5. Interrupt register bit assignment
4.8.6. Soft interrupt set and soft interruptclear registers
4.9. Voltage control registers
4.10. SDRAM SPD memory
5. Using Core Modules with an Integrator/AP
5.1. About the system architecture
5.1.1. Configuring little or big-endian operation
5.2. Module ID selection
5.2.1. Module address decoding
5.3. Top level memory map
5.3.1. Global SDRAM access
5.3.2. Access arbitration
5.4. Register and memory overview
5.4.1. CM control register for Integrator/AP
5.5. System bus bridge
5.5.1. Processor accesses to the system bus
5.5.2. Motherboard accesses to SDRAM
5.5.3. Multiprocessor support
5.5.4. System bus signal routing
5.6. Reset controller
5.6.1. Reset control signals
5.6.2. Software resets
5.7. Interrupt control
6. Using Core Modules with an Integrator/CP
6.1. About the system architecture
6.1.1. Integrator/CP system buses
6.1.2. Configuring little or big-endian operation
6.2. Module ID selection and interruptrouting
6.3. Top level memory map
6.3.1. Physical location of memory chips
6.3.2. Configurable area of memory map
6.3.3. Baseboard flash memory
6.3.4. Memory timing
6.4. Programmable logic
6.4.1. Baseboard system support PLD
6.4.2. System controller FPGA
6.4.3. HDL files
6.5. Register and memory overview
6.5.1. CM control register for Integrator/CP
6.6. Peripherals and interfaces
6.6.1. Clock control
6.6.2. Counter/timers
6.6.3. Real-time clock
6.6.4. UARTs
6.6.5. Keyboard and mouseinterface
6.6.6. MMC interface
6.6.7. Audio interface
6.6.8. Touchscreen controller interface
6.6.9. Display interface
6.6.10. Ethernet interface
6.7. Reset controller
6.7.1. Reset control signals
6.7.2. Software resets
6.8. Interrupt control
6.8.1. Interrupt controllers
6.8.2. Interrupt routing between Integratormodules
6.8.3. CP image interruptcontrol registers
6.8.4. Handling interrupts
A. Signal Descriptions
A.1. HDRA
A.2. HDRB
A.2.1. HDRB socket pinout
A.2.2. HDRB plug pinout
A.2.3. Through-board signal connections
A.2.4. HDRB signal descriptions
A.3. Trace connector pinout
A.4. Logic analyzer connectors
A.4.1. HADDR connector
A.4.2. CONTROL connector
A.4.3. HRDATA connector
A.4.4. HWDATA connector
B. Specifications
B.1. Electrical specification
B.1.1. Bus interface characteristics
B.1.2. Current requirements
B.2. Timing specification
B.2.1. Core module timing and the AMBA Specification
B.2.2. Timing parameter tables
B.2.3. Notes on FPGA timing analysis
B.3. Mechanical details
C. Features specific to the CM1136JF-S
C.1. Introduction to the CM1136JF-S
C.1.1. Platform support
C.1.2. Boot Monitor
C.2. ARM1136JF-S test chip characteristics
C.2.1. Clocks
C.2.2. AHB matrix and memories block
C.2.3. On-chip memory-mapped peripherals
C.2.4. External AHB interface
C.2.5. AHB address map
C.2.6. Block disables
C.2.7. AHB submodules
C.2.8. AHB slaves and support blocks
C.2.9. AHBPCAPT slave registers
C.2.10. Vectored Interrupt Controller (VIC) block

List of Figures

1.1. Integrator/CM946E-S and CM966E-Slayout
1.2. Integrator/CM926EJ-S, CM1026EJ-S,and CM1136JF-S layout
1.3. Core module block diagram
1.4. Links and indicators for the CM946E-Sand CM966E-S
1.5. Links and indicators for the CM926EJ-S,CM1026EJ-S, and CM1136JF-S
1.6. Test points (CM946E-S and CM966E-S)
1.7. Test points (CM926EJ-S, CM1026EJ-S,and CM1136JF-S)
2.1. Power connector
2.2. Multi-ICE connection to a core module
2.3. Alternative connector layout (CM946E-Sand CM966E-S)
2.4. Connector layout for CM926EJ-S, CM1026EJ-S,and CM1136JF-S
2.5. Connecting Trace
2.6. Connecting Multi-ICE to the traceport adapter board
2.7. Assembled Integrator system
2.8. Assembled Integrator system
3.1. FPGA configuration
3.2. CM946E-S and CM966E-S clock generator
3.3. CM926EJ-S clock generator
3.4. JTAG connector, CONFIG link, and LED
3.5. JTAG data path
3.6. JTAG clock path
3.7. Multi-ICE connector pinout
3.8. Trace connection
3.9. Voltage control and monitoring
4.1. Example memory maps
4.2. Configurable memory map for CM926EJ-S,CM1026EJ-S, and CM1136JF-S
4.3. Configurable memory map for CM946E-Sand CM966E-S
4.4. SSRAM aliases
4.5. Repeat DRAM mapping
4.6. Core module ID
4.7. Core module status register
4.8. Core module oscillator register
4.9. Core module lock register
4.10. Core module auxiliary oscillatorregister
4.11. SDRAM status and control register
4.12. Core module initialization register
4.13. Interrupt control
5.1. FPGA functional diagram
5.2. Top-level memory map
5.3. Core module local and alias addresses
5.4. Core module control register
5.5. Processor writes to the system bus
5.6. Processor reads from the system bus
5.7. System bus writes to SDRAM
5.8. System bus reads from SDRAM
5.9. Signal rotation on HDRB (Integrator/AP)
5.10. Core module reset controller
5.11. Interrupt architecture (AP image)
6.1. Integrator/CP system architecture
6.2. Bus routing between baseboard, coremodule, and logic module
6.3. APB peripherals
6.4. Top-level memory map
6.5. Top-level memory map
6.6. Baseboard PLD
6.7. System controllerFPGA block diagram
6.8. CM_CTRL
6.9. Core module reset controller
6.10. Interrupt architecture (CP image)
6.11. Interrupt signal routing
A.1. HDRA plug pin numbering
A.2. HDRB socket pin numbering
A.3. HDRB plug pin numbering
A.4. AMP Mictor connector
B.1. Board outline
C.1. AHB matrix and memories

List of Tables

1.1. LED functional summary
1.2. Test point functions (CM946E-S and CM966E-S)
1.3. Test point functions (CM926EJ-S, CM1026EJ-S, and CM1136JF-S)
3.1. Controllable processor configuration signals
3.2. Fixed processor configuration signals
3.3. Image selection signals
3.4. JTAG signal description
3.5. ETM resources
3.6. Link LK1 positions
4.1. Overview of core module memory map
4.2. Effect of SSRAM mode 0 and mode 1
4.3. Core module status, control, and interrupt registers
4.4. CM_ID register bit descriptions
4.5. CM_STAT register
4.6. CM_OSC register
4.7. CM_LOCK register
4.8. CM_AUXOSC register
4.9. CM_SDRAM register
4.10. CM_INIT register
4.11. Core module flag registers
4.12. Interrupt controller registers
4.13. IRQ and FIQ register bit assignment
4.14. IRQ register bit assignment
4.15. CM_VOLTAGE_CTL0 register (0x80)
4.16. CM_VOLTAGE_CTL1 register (0x84)
4.17. CM_VOLTAGE_CTL2 register (0x88)
4.18. CM_VOLTAGE_CTL3 register (0x8C)
4.19. SPD memory contents
5.1. Core module address decode
5.2. System control register map
5.3. CM_CTRL register
5.4. Reset signal descriptions
5.5. Core module interrupts
6.1. Example of 32KB TCM and SSRAM mode 0
6.2. Example of TCM disabled and SSRAM mode 0
6.3. Example of TCM disabled and SSRAM mode 1
6.4. Example of 32KB TCM enabled and SSRAM mode 0
6.5. Example of TCM disabled and SSRAM mode 0
6.6. Example of TCM disabled and SSRAM mode 1
6.7. Example of 128KB TCM enabled and SSRAM mode 0
6.8. Wait states for memory access
6.9. CM image functional block HDL file descriptions
6.10. System control register map
6.11. CM_CTRL register
6.12. Reset signal descriptions
6.13. Primary interrupt register addresses
6.14. Primary interrupt register bit assignments
6.15. Secondary interrupt register addresses
A.1. Bus bit assignment (for an AMBA AHB bus)
A.2. Signal cross-connections (example)
A.3. HDRB signal description (AHB)
A.4. Trace connector A pinout
A.5. Trace connector B (J15) pinout
A.6. HADDR (J9)
A.7. Control (J12)
A.8. HRDATA (J11)
A.9. HWDATA (J10)
B.1. Core module electrical characteristics
B.2. Current requirements (maximum)
B.3. Clock and reset parameters
B.4. AHB slave input parameters
B.5. AHB slave output parameters
B.6. Bus master input timing parameters
B.7. Bus master output timing parameters
C.1. Clock Generator Control Register
C.2. Core Module Oscillator Register
C.3. AHB interfaces
C.4. Test chip address map
C.5. External control inputs
C.6. AHB slaves
C.7. ARM1136JF-S AHBPCAPT Slave Registers
C.8. Pin Capture Register bit allocation
C.9. Test Chip Memory Size Register
C.10. Valid test chip RAM sizes
C.11. Contents of each AHB Port Register
C.12. Test Chip Control Register
C.13. ETM11RV Pin Capture1 Register
C.14. ETM11RV Pin Capture2 Register
C.15. ETM11RV Pin Capture3 Register
C.16. ETM11RV Pin Control1 Register
C.17. ETM11RV Pin Control2 Register
C.18. ETM11RV Pin Control3 Register
C.19. ETM11RV Pin Control4 Register
C.20. EtmInputSel[1:0] encoding
C.21. EtmInputSel[3:2] encoding
C.22. EtmInputSel[5:4]
C.23. Configuration Register
C.24. Test chip interrupt routing

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Neither the whole nor any part of the information containedin, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permissionof the copyright holder.

The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM Limited in goodfaith. However, all warranties implied or expressed, including butnot limited to implied warranties of merchantability, or fitnessfor purpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt frompart 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The Integrator generates, uses, and can radiate radio frequencyenergy and may cause harmful interference to radio communications.However, there is no guarantee that interference will not occurin a particular installation. If this equipment causes harmful interferenceto radio or television reception, which can be determined by turningthe equipment off or on, you are encouraged to try to correct theinterference by one or more of the following measures:

  • ensure attached cables donot lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment andthe receiver

  • connect the equipment into an outlet on a circuitdifferent from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technicianfor help

Note

It is recommended that wherever possible shielded interfacecables be used.

Revision History
Revision A 26September 2000 New document
Revision B 9November 2002 Second release
Revision C 19November 2003 Third release. Updated clock registerinformation
Revision D 2March 2004 Added CM1026 and CM1136
Revision E 19April 2005 Fourth release. Corrected contents forCM1136JF-S cache, HBUSREQ status, HCLK reset, and SRAM FIFO
Copyright © 2000-2005 ARM Limited. All rights reserved. ARM DUI 0138E
Non-Confidential