13.18.2. Statistics for uncached Harvard processors

When simulating an uncached Harvard architecture processor such as the ARM926EJ-S, the following information is displayed:

Reference Points

The name you specify to identify each line of statistics that you add.

Instructions

The number of program instructions executed.

Core_Cycles

The total number of processor clock ticks, including stalls because of interlocks and instructions that take more than one cycle.

ID_Cycles

Cycles in which both the instruction bus and the data bus were active.

IBus_Cycles

Cycles in which the instruction bus was active and the data bus was idle.

Idle_Cycles

Cycles in which both the instruction bus and the data bus were idle.

DBus_Cycles

Cycles in which the data bus was active and the instruction bus was idle.

Total

The sum of cycles on the memory bus.

See also

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