The CPSR and SPSR register entries include a settings string showing the current settings of the flags in the register, for example:
CPSR zncvqIFtSVC
You change the flags by using the PSR dialog box.
To change values for the CPSR or an SPSR register:
To change a specific SPSR register, expand the appropriate register bank. Otherwise, skip this step. The rest of this procedure describes how to change the CPSR register.
Double-click on the CPSR register, shown in Figure 14.5.
The PSR dialog box is displayed, shown in Figure 14.6.
Change the settings as required:
To change the
Flags,InterruptorState, click the appropriate button.When a button is depressed, the corresponding bit in the CPSR register is set. The letter in the register field that corresponds to the bit changes to uppercase. That is, uppercase letters identify bits that are set.
To change the
Mode, select the required mode from the drop-down list.
The new settings are displayed as text and hexadecimal format in the
Current valuegroup.Click OK to apply the changes. The register value is colored blue.
For ARM® architecture-based
processors that have the extra Q bit (signifying saturation) in
the program status register, the dialog box has a Q button
in the Flags group. Figure 14.8 shows an example.
For ARM architecture-based processors that support Jazelle® bytecode or Thumb®-2EE there are extra bits:
For processors that support Jazelle bytecode, a J bit in the program status register signifies Jazelle state. Also the PSR dialog box has a J button in the
Stategroup.For processors that support Thumb-2EE, a T bit in the program status register signifies ThumbEE state. Also the PSR dialog box has a T button in the
Stategroup.
To set the State for processors that support both Jazelle bytecode and Thumb-2EE, set the button states shown in Table 14.1.
Table 14.1. CPSR and SPSR register T and J bit states
| State | T bit state | J bit state |
|---|---|---|
| ARM | 0 (t) | 0 (j) |
| Thumb | 1 (T) | 0 (j) |
| Bytecode | 0 (t) | 1 (J) |
| ThumbEE | 1 (T) | 1 (J) |
For Thumb-2EE processors there is also:
a Control group containing:
an E button (signifying data endianness)
an A button (signifying imprecise data abort disable).
a Greater than or Equal group of buttons for the GE[3:0] bits used by the
SIMDinstructions.
Figure 14.7 shows an example of the CPSR register for the ARM1136JF-S™. Figure 14.8 shows the corresponding PSR dialog box.
For ARM architecture-based processors that support If Then, such as Cortex™-A8, there is an extra IT field in the program status register.
Figure 14.9 shows an example of the CPSR register for the Cortex-A8. Figure 14.10 shows the corresponding PSR dialog box.
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