7.11.5. Defining memory for a three processor multimedia development platform

A more complex example configuration, shown in Figure 7.19, shows the address spaces of three processors sharing two memory regions.

Each entry in the Advanced_Information section of the board file describes the memory layout of a processor as one or more segments. For each processor and for each segment, the board file must include:

Figure 7.19. Example of a shared memory configuration

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The details of the settings that you must make in your Connection Properties window to configure the three processors are shown in Figure 7.19. You must start by creating a Board/Chip definition file, similar to the CP.bcd shown in Figure 7.20, and then referencing it from the board file by using the BoardChip_name setting in the CONNECTION= group.

Figure 7.20. Editing the memory block in the CP Board/Chip definition file

Editing the memory block in the CP Board/Chip definition file

To configure RealView Debugger for the target shown in Figure 7.19, you must set up several memory blocks. Each processor has a memory block for its private area and a block for a shared communication area. The ARM920T processor has two shared areas, so it has three memory blocks. You must create a separate group of settings for each processor.

Procedure for creating processor-specific connection settings

To create a separate Advanced_Information group for each processor:

  1. Expand the Advanced_Information group for the Debug Configuration.

  2. Create a new Advanced_Information block, and remove the Default block:

    1. Right-click on Advanced_Information in the left pane to display the context menu.

    2. Select Make New... from the context menu to open a rename dialog box.

    3. Enter ARM966EJ-S_2.

    4. Click Create.

    5. Right-click on the Default block in the left pane.

    6. Select Delete.

    Note

    RealView Debugger matches this name with the connection name when you connect to the processor. Therefore, only the Advanced_Information group settings that match the processor are assigned to that connection.

  3. Make a copy of the ARM966EJ-S_2 group and name it ARM920T_0.

  4. Make a copy of the ARM920T_0 group and name it ARM940T_1.

    You now have a separate Advanced_Information block for each of the processors on your development platform.

  5. Expand each processor group in turn, and set up the Memory_block with the following settings:

    ARM966EJ-S_2 group

    Create two sub-blocks named LocalMem and GfxMem in the Memory_block group. Change the settings in the groups as follows:

    LocalMem

    Set the following:

    Start=0
    Length=0x10000
    Description="Local program memory"
    
    GfxMem

    Set the following:

    Start=0x10000
    Length=0x10000
    Description="Frame Buffer"
    

    Set the following in the Attributes group:

    Shared=direct
    Shared_id=1
    
    ARM920T_0 group

    Create three sub-blocks named LocalMem, GfxMem, and CommsMem in the Memory_block group. Change the settings in the groups as follows:

    LocalMem

    Set the following:

    Start=0
    Length=0x40000
    Description="Local program memory"
    
    GfxMem

    Set the following:

    Start=0x40000
    Length=0x10000
    Description="Frame Buffer"
    

    Set the following in the Attributes group:

    Shared=direct
    Shared_id=1
    
    CommsMem

    Set the following:

    Start=0x80000
    Length=0x1000
    Description="Shared IPC memory"
    

    Set the following in the Attributes group:

    Shared=direct
    Shared_id=2
    
    ARM940T_1

    Create two sub-blocks named LocalMem and CommsMem in the Memory_block group. Change the settings in the groups as follows:

    LocalMem

    Set the following:

    Start=0
    Length=0x40000
    Description="Local program memory"
    
    CommsMem

    Set the following:

    Start=0x80000
    Length=0x1000
    Description="Shared IPC memory"
    

    Set the following in the Attributes group:

    Shared=direct
    Shared_id=2
    
  6. Select File → Save and Close from the menu to save your changes and close the Connection Properties window.

Observations on the three processor example

In the three processor example, the memory map for each processor is defined using the target name (for example, ARM920T) followed by an underscore and the TAP controller ID for that processor (for example, _0). Including the TAP number in addition to the processor name enables you to specify the exact processor if your development platform using more than one processor of the same type.

Within each processor memory block, some common properties of processor memory are defined, for example, defining the bus width using Access_size. These properties are inherited by the other memory specification blocks.

Specific properties, including start address and length of the memory regions, are defined for each of the memory regions. The regions are called LocalMem, CommsMem and GfxMem. In this example, the CommsMem region appears at the same place in the memory map of each of the processors accessing it, but the GfxMem does not. Where a shared region appears, in a given processor memory map, it is a function of the hardware memory address decoders on the target. It does not matter to RealView Debugger whether the shared regions map to the same addresses or to different addresses on the processors sharing them.

The default memory sharing state is not shared (indicated by the entry Shared=none), so the LocalMem definition does not have to state this. However, the CommsMem and GfxMem regions are shared, so the two attributes Shared and Shared_id must be specified for both regions. The value of Shared is one of:

none

The memory region is not shared.

direct

The memory region is shared.

The memory region share IDs used in this example are:

1

the video buffer memory

2

the interprocessor communications memory.

However, you can use any integer value in the range 0 to 65535.

Note

Although there is normally only one shared memory device, shared resources are described as part of the processor memory map, and not by physical device. RealView Debugger requires that the shared memory device is described at least twice, once for each processor sharing it. If you describe the device for only one processor, then RealView Debugger is unable to automatically update the views of the shared memory region for each processor.

Using Debug Interface units

The multiprocessor configurations described in this section can be implemented using a single DSTREAM or RealView ICE Debug Interface unit if all processors are on the same JTAG chain. When connected to multiple processors, the connection properties inherent in the interface apply to all the connections.

The configurations described can be also achieved using multiple DSTREAM or RealView ICE units to the same development platform.

Note

Although multiple target connections can be established using RVISS and ISSM models, the simulated targets cannot share memory, even if you configure a shared memory region. However, multiprocessor Model Library, Model Process, RTSM, and SoC Designer models might contain memory that can be shared.

See also

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