F.1.2. SWD timing requirements

This section describes the timing requirements for the SWD interface when the clock is sourced from the RVI.

The RVI connects to the serial wire-enabled target using the LVDS probe. The interface uses only two lines, but for clarity the diagrams shown in Figure F.1 separate the SWDIO line to show when it is driven by either the RVI probe or target.

Figure F.1. SWD timing diagrams


The probe outputs data to SWDIO on the falling edge of SWDCLK. The probe captures data from SWDIO on the rising edge of SWDCLK. The target outputs data to SWDIO on the rising edge of SWDCLK. The target captures data from SWDIO on the rising edge of SWDCLK.

Table F.2 shows the timing requirements for the SWD.

Table F.2. SWD timing requirements

ParameterMinMaxDescription
Thigh10ns500μsSWDCLK HIGH period
Tlow10ns500μsSWDCLK LOW period
Tos-5ns5nsSWDIO Output skew to falling edge SWDCLK
Tis4ns-Input Setup time required between SWDIO and rising edge SWDCLK
Tih1ns-Input Hold time required between SWDIO and rising edge SWDCLK

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