4.2.6. Configuring CoreSight cores

This section describes the configuration items to be considered when dealing with CoreSight components.

Configuring CoreSight cores

Configuration Item: “CoreSight AP Index” (CORESIGHT_AP_INDEX)

The index of the AP in the DAP that must be used to access the CoreSight debug registers for the CoreSight component.

Configuration Item: “CoreSight Base Address” (CORESIGHT_BASE_ADDRESS)

The base address of the CoreSight debug registers on the bus accessed through the AP as specified in the “CoreSight AP Index” configuration item.

Configuring non-Cortex cores in CoreSight systems

Non-Cortex cores in a CoreSight system are generally connected to the JTAG-AP port in the DAP. RealView ICE v3.1 supports ARM11x6 series cores connected to the JTAG-AP. To debug these cores, yours must use the JTAG-AP versions of the ARM11x6 templates provided by RealView ICE v3.1.

Configuration Item: “CoreSight ETM” (CORESIGHT_ETM)

In systems where a non-Cortex core (for example, ARM1136JF-S) is connected to a DAP through the JTAG-AP port, there are two possible ways in which the ETM in such a system can be provided. The first is the non-Cortex method, whereby the ETM is accessible through an internal scan chain on the core. The second is whereby the ETM is accessible through the APB-AP on the DAP. If the system has the ETM connected through the DAP, then this configuration item must be set to True.

Configuration Item: “CoreSight AP Index” (CORESIGHT_AP_INDEX)

The index of the JTAG-AP in the DAP that must be used to access the CoreSight debug registers for the CoreSight component.

Configuration Item: “JTAG-AP Port index for core” (JTAG_PORT_ID)

The index of the JTAG-AP Multiplexor port to which the CoreSight component is connected.

Configuration Item: “Fast memory download” (FAST_MEM_WRITES)

The Fast Memory Download option is available for those targets where the DAP and the Core are running fast enough to handle the data being sent to them by the RealView ICE unit without the RealView ICE unit having to check that each individual transaction with the DAP has been successful. The core is behind the DAP, so all core accesses have to go through the DAP. As a guide, this setting must not be set for those targets that are FPGA-based.

Note

With this option set, error checking is disabled. If any errors occur, you are not informed. If problems are encountered when downloading images, unchecking this option resolves them.

Reset options in RealView ICE

Configuration Item: “Allow ICE to latch System Reset” (AllowICELatchSysRst)

Set to True if you want to enable the ICE to latch system reset. This enables the RealView ICE unit to set up any hardware debug resources it requires to ensure that the core(s) can be stopped as soon as system reset is de-asserted.

Set to False if you do not want to enable the ICE to latch system reset. You must only do this if you are concerned about accurate reset hold times. Enableing system reset to be latched by the ICE can extend the system reset hold time.

The default setting is True.

Configuration Item: “Allow ICE to perform TAP Reset” (AllowICETAPReset)

Set to True if you want to enable the ICE to assert TAP reset when it deems necessary. This enables the ICE to reset the debug hardware logic and re-program it into a known state, for example, during the system reset handling phase.

Set to False if you do not want to enable the ICE to assert TAP reset. Although this is benign, on some systems TAP reset can have side effects that are not linked solely to the debug hardware. If this is the case, you might want to prevent the ICE from asserting TAP reset.

The default setting is True.

Configuring CoreSight systems with multiple devices per JTAG-AP multiplexor port

Although JTAG-AP supports multiple cores through a multiplexor wrapper, it is recommended that only one core is connected to each multiplexor port. If, however, you have a system that connects multiple devices to a single JTAG-AP multiplexor port, RealView ICE still supports it.

To debug CoreSight systems that have cores connected to the DAP through JTAG-AP, RealView ICE must know the pre-bits and post-bits for JTAG operations. Figure 4.20 shows a hypothetical scan chain that could be connected to a JTAG-AP.

Figure 4.20.  scan chain connected to a JTAG-AP


Multiple devices on the scan chain are connected in series, with data flowing serially from TDO to TDI. This means that debugging a given target in the chain requires that certain pre-scan and post-scan bits are used to ensure that the other devices are not affected by the data directed at the target device, and that the data is positioned correctly in the serial scan for the target device.

To debug this system, the following four configuration items must be set.

Configuration Item: “Pre-scan IR bits for Devices after the core on the JTAG-AP scanchain” (JTAG_AP_IR_PRE_BITS)

This is the total length of the JTAG instruction registers (IRs) for devices appearing between the core being configured and the CSTDO input on the JTAG-AP port. In Figure 4.20, the three devices that appear between the target core and the CSTDO input on the JTAG-AP port have IR lengths 5, 7 and 11, respectively. Therefore, this value must be set to 23.

Configuration Item: “Post-scan IR bits for Devices before the core on the JTAG-AP scanchain” (JTAG_AP_IR_POST_BITS)

This is the total length of the JTAG IRs for devices appearing between the CSTDI output on the JTAG-AP port and the core being configured. In Figure 4.20 the two devices that appear between the CSTDI output on the JTAG-AP port and the core being configured have IR lengths 2 and 3, respectively. Therefore, this value must be set to 5.

Configuration Item: “Pre-scan DR bits for Devices after the core on the JTAG-AP scanchain” (JTAG_AP_DR_PRE_BITS)

This is the total number of devices appearing between the core being configured and the CSTDO input on the JTAG-AP port. In Figure 4.20, there are three devices that appear between the core being configured and the CSTDO input on the JTAG-AP port. Therefore, this value must be set to 3.

Configuration Item: “Post-scan DR bits for Devices before the core on the JTAG-AP scanchain” (JTAG_AP_DR_POST_BITS)

This is the total number of devices appearing between the CSTDI output on the JTAG-AP port and the core being configured. In Figure 4.20, there are two devices that appear between the CSTDI output on the JTAG-AP port and the core being configured. Therefore, this value must be set to 2.

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