A.3. JTAG port timing characteristics

This section describes the timing characteristics of the RealView ICE unit:

These timing characteristics must be considered if you design a target device or board and want to be able to connect RealView ICE at a particular TCK frequency. The characteristics relate to the RealView ICE hardware. You must consider them in parallel with the characteristics of your target.

Figure A.2. JTAG port timing diagram


In a JTAG device that fully complies to IEEE1149.1-2001, TDI and TMS are sampled on the rising edge of TCK, and TDO changes on the falling edge of TCK. To take advantage of these properties, RealView ICE samples TDO on the rising edge of TCK and changes its TDI and TMS signals on the falling edge of TCK. This means that with a fully compliant target, issues with minimum setup and hold times can always be resolved by decreasing the TCK frequency, because this increases the separation between signals changing and being sampled.

Note

There are no separate timing requirements for adaptive clocking mode, because the minimum Tbsch and Tbscl times are identical and are the same as for non-adaptive clocking. Tbsis and Tbsih are relative to RTCK rising, and not TCK rising, as RTCK is used to sample TDO in adaptive clocking mode.

The only real timing difference is that in adaptive mode, RealView ICE samples TDO on the rising edge of RTCK and not TCK, so TDO timing is relative to RTCK.

Table A.2 shows the timing requirements for the JTAG A port, measured open circuit (no target connection, except for 3.3V reference on VTref) with the supplied JTAG cable connected.

Table A.2. RealView ICE JTAG A timing requirements

ParameterMinMaxDescription
Tbscl50ns500μsTCK LOW period
Tbsch50ns500μsTCK HIGH period
Tbsod-6.0nsTDI and TMS valid from TCK (falling)
Tbsis15.0ns-TDO setup to TCK (rising)
Tbsih6.0ns-TDO hold from TCK (rising)

Table A.3 shows the timing requirements for the JTAG B port, measured open circuit (no target connection, except for 3.3V reference on VTref) with no cable connected.

Table A.3. RealView ICE JTAG B timing requirements

ParameterMinMaxDescription
Tbscl10ns500μsTCK LOW period
Tbsch10ns500μsTCK HIGH period
Tbsod-3.2nsTDI and TMS valid from TCK (falling)
Tbsis6.2ns-TDO setup to TCK (rising)
Tbsih4.5ns-TDO hold from TCK (rising)

Note

  • The RealView ICE software enables you to change the TCK frequency. The TCK LOW:HIGH mark-space ratio is always 50:50. The other parameters must be considered with the specific values of Tbscl and Tbsch that you have chosen. The default values for an autoconfigured single-TAP system are, nominally, Tbscl=50ns and Tbsch=50ns.

  • Tbsod is the maximum delay between the falling edge of TCK and valid levels on the TDI and TMS RealView ICE output signals. The target samples these signals on the following rising edge of TCK and so the minimum setup time for the target, relative to the rising edge of TCK, is Tbscl–Tbsod.

  • Tbsis is the minimum setup time for the TDO input signal, relative to the rising edge of TCK when RealView ICE samples this signal. The target changes its TDO value on the previous falling edge of TCK and so the maximum time for the target TDO level to become valid, relative to the falling edge of TCK, is Tbscl–Tbsis.

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