5.2.1. Enabling semihosting

When using RealView ICE, semihosting is handled by emulating a SVC exception handler using breakpoints. You can modify this semihosting mechanism using the following RealView Debugger internal registers:


By default, this variable is set to 1 to enable breakpoint semihosting but you can set it to the following values:


Disables semihosting.


Enables semihosting.


This variable controls the location of the breakpoint set by the RealView ICE software to detect a semihosted SVC. It is set to 8 by default, unless you have specified that high vectors are in use.

In RealView Debugger, these internal registers are accessed using the Debug tab in the Register pane of the Code window. See Using the Debug tab of the RealView Debugger Register pane and the RealView Debugger documentation suite for more information (see ARM publications).


Semihosting involves setting a breakpoint either on the SVC vector or somewhere else in cooperation with your own SVC handler, depending on the value of SEMIHOST_VECTOR.


Cortex-M3 does not provide vector catch on SVC. For details on Cortex-M3 semihosting see Cortex-M3 semihosting.

When the breakpoint is hit, RealView ICE interprets it as a semihosting request:

  • the processor registers and memory are read as required to decode the request

  • the request is executed on the host

  • the return value is placed in register R0 and, when required, memory is modified

  • the pc is modified so that the next instruction is the instruction following the SVC

  • execution is resumed.

By default, the ARM C library code uses semihosting for I/O operations and for certain system-specific settings, such as SP value.


Using RealView ICE semihosting with systems that include time-sensitive interrupt-driven software is not recommended. The processor is halted while a semihosting operation is performed, and interrupts are therefore missed.

The breakpoint on the SVC vector uses breakpoint resources that might be required for other purposes.

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