4.2.7. Configuring devices

Before you can configure a device on a particular scan chain, you must ensure that the RVConfig dialog box displays the controls for that device. To do this, select the node for the device in the tree diagram, as shown in Figure 4.21.

Figure 4.21. Displaying the device controls

Displaying the device controls

Alternatively, select the Devices node in the tree diagram so that the control pane displays the scan chain controls (see Figure 4.14). Now select the required device in the scan chain, and click the Configure button located in the Devices panel.

Depending on the device that you have selected, some or all of the following controls might appear:

Note

If you want to configure CoreSight systems, see the RealView Debugger User Guide.

The Code Sequence settings

The Code Sequences Enabled facility enables you to set code sequence default values and sizes without enabling them.

Note

Code sequences are disabled by default, so you must enable these as required.

The Code Sequence Address and the Code Sequence Size (bytes) values set the virtual address and the size of an area of memory on the target that the RealView ICE software can use. This area of memory must be:

  • unused by the target

  • readable

  • writable

  • non-cacheable (for cached targets)

  • at least 128 bytes in size.

The RealView ICE software downloads code sequences to this area to perform various tasks, such as cleaning the cache (see Cached data) and accessing certain CP15 registers on targets such as the ARM920T™ and ARM1136JF-S. It does not preserve the contents of this area.

Note

You must ensure that the Code Sequence Address and the Code Sequence Size (bytes) values are correctly set up before you attempt to write to any of the Cache Operations or TLB Operations in the RealView Debugger Register pane. If you do not set these values correctly, RealView Debugger gives one or more of the following errors:

  • Error V28305 (Vehicle): Memory operation failed

  • Warning: Code sequence memory area size error

  • Unable to load code sequence into defined memory area.

The Code Sequence Timeout (ms) value sets a timeout for execution of the uploaded code sequence. For most targets, a 500ms timeout is sufficient.

To change the code sequence settings, type the required value into the appropriate text box.

Bypass memory protection when in debug

If Bypass memory protection when in debug is selected, any memory protection provided by hardware (such as a memory management or protection unit) is bypassed whenever the target hardware enters debug state. This enables you to access protected memory so that you can set software breakpoints in it, or alter its contents.

Ignore bad JTAG IDCODE

By default, RealView ICE reads the device JTAG IDCODE to verify the integrity of the JTAG connection. The JTAG standard restricts the JTAG IDCODE value to be 32 bits long and requires the least significant bit to be a 1. If RealView ICE reads an invalid (bad) JTAG IDCODE, it assumes that the JTAG connection is not functioning properly, and fails the attempt to connect to the core.

If the device you want to connect to has an invalid JTAG IDCODE, set this option to True by selecting the checkbox. This instructs RealView ICE to enable connection to the core even if it detects that the JTAG IDCODE is invalid.

Use LDM or STM for memory access

This option is available if you are using an ARM926EJ-S, ARM946E-S, or ARM966E-S processor. Set this option to True (checked) if you want to use Load Multiple Instructions (LDM) or Store Multiple Instructions (STM) to access target memory. You might have to set this option to False (unchecked) if you have a peripheral that is not fully compatible with the AMBA™ 2.0 standard, because in such cases LDM and STM might not be compatible.

JTAG Timeouts Enabled

By default, JTAG timeouts are enabled. You must deselect this option to disable JTAG timeouts when RealView ICE is connected to a core using a low clock speed and adaptive clocking. This is because RealView ICE cannot detect the clock speed when adaptive clocking is used, and therefore cannot scale its internal timeouts. If a JTAG timeout occurs, the JTAG is left in an unknown state and RealView ICE cannot operate correctly without reconnecting to the core.

Fast Memory Download

By default, this option is False. This configuration item is used to control an optimization that speeds up memory downloads. It achieves this by not checking whether the memory operation has completed before starting the next one, and assumes that it can complete safely during the interval before the next operation starts.

On a number of cores, this assumption does not hold. These are:

  • ARM7EJS-JTAG-AP

  • ARM9EJS-JTAG-AP

  • ARM926EJS-JTAG-AP

  • ARM946ES-JTAG-AP

  • ARM966ES-JTAG-AP

  • ARM968ES-JTAG-AP

Software breakpoint mode

This option enables you to configure how RealView ICE handles software breakpoints. Select the required breakpoint mode:

AUTO

This is the default mode for all templates:

  • If the core being debugged supports BKPT instructions, RealView ICE automatically uses the BKPT instruction for software breakpoints.

  • If the core being debugged does not support BKPT instructions, RealView ICE uses the watchpoint unit resource when you set a software breakpoint. In this case, RealView ICE automatically frees the watchpoint unit resource when all software breakpoints are cleared.

NONE

When this mode is selected, you cannot set software breakpoints. If you attempt to set a software breakpoint, RealView ICE gives an error message telling you that there are no free resources to set the breakpoint.

WATCHPOINT

This option instructs RealView ICE to use one watchpoint unit to provide software breakpoint instructions, whether or not the core being debugged supports BKPT instructions. Select this option if the core supports BKPT instructions but you want to use a watchpoint unit.

BKPT

This option instructs RealView ICE to use the BKPT instruction to provide software breakpoint instructions, whether or not the core supports this instruction. Select this option if you want to make sure that no watchpoints are used.

Allow execution with T-Bit Clear

For Cortex-M1 and Cortex-M3 cores, this option enables you to attempt to execute in ARM state cores that only support Thumb mode.

Clear break HW on connect

This option is available if you are using an ARM11 processor. The ARM11 processor does not clear the breakpoint hardware on connection. Set this option to True to instruct RealView ICE to perform this operation each time you connect.

Post Reset State

Set Post Reset State to the required state for the target hardware:

Running

The target hardware is running.

Stopped

This option controls the state of a core after a reset. Is is only available for devices that are capable of running (such as ARM cores). Each device on the scan chain does not have to be set to the same value, so it is valid to have one core running and another stopped.

If you want to connect to a running target without performing a reset and without stopping the target, you must do both of the following:

  • In RealView ICE, set the Post Reset State to Running.

  • In RealView Debugger, connect using the Connect (Connection Modes) of No Reset / No Stop. For information on setting the connection mode, see the RealView Debugger Target Configuration Guide.

Configuring SecurCore behavior when stepping instructions and the core clock stops

Configuration Item: “No error if step-instr can’t stop” (NO_ERROR_ON_STEPRUN)

Controls generation of error messages if a step instruction (stepi) operation fails because of a timeout attempting to stop the core after a step is complete. This can occur on the SecurCore if an instruction execution results in the core clock being disabled through CLKEN. The core appears to be in a running state. The default setting of True results in no error appearing if an instruction step results in the core running. Setting the item to False results in an error dialog appearing in RealView Debugger.

Configuring TrustZone enabled core behavior when debug privileges are reduced

Configuration Item: “Ignore debug privilege errors when starting core” (IGNORE_START_DEBUG_PRIV_FAIL)

When the SPIDEN line is changed from HIGH to LOW, the following errors might be seen:

  • Insufficient debug privilege to restore core state for restart.

  • Insufficient debug privilege to write software breakpoint to memory.

These errors can be suppressed by setting the “Ignore debug privilege errors when starting core” (IGNORE_START_DEBUG_PRIV_FAIL) configuration item.

When this configuration item is set, RealView ICE starts the core running, even though the breakpoints/core state is incorrect.

When this configuration item is NOT set, RealView ICE refuses to start the core, and reports the errors.

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