The items in this glossary are listed in alphabetical order, with any symbols and numerics appearing at the end.

Access-provider connection

A debug target connection item that can connect to one or more target processors. The term is normally used when describing the RealView Debugger Connection Control window.

Adaptive clocking

A technique in which a clock signal is sent out by RealView ICE and it waits for the returned clock before generating the next clock pulse. The technique enables the RealView ICE run control unit to adapt to differing signal drive capabilities and differing cable lengths.

Address breakpoint

A type of breakpoint. See Breakpoint.

Advanced High-performance Bus (AHB)

The AMBA Advanced High-performance Bus system connects embedded processors such as an ARM core to high-performance peripherals, DMA controllers, on-chip memory, and interfaces. It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance.

See Also Advanced Microcontroller Bus Architecture and AHB-Lite.

Advanced Microcontroller Bus Architecture (AMBA)

AMBA is the ARM open standard for multi-master on-chip buses, capable of running with multiple masters and slaves. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC). It aids in the development of embedded processors with one or more CPUs or signal processors and multiple peripherals. AMBA complements a reusable design methodology by defining a common backbone for SoC modules. AHB conforms to this standard.


See Advanced High-performance Bus.


AHB-Lite is a subset of the full AHB specification. It is intended for use in designs where only a single AHB master is used. This can be a simple single AHB master system or a multi-layer AHB system where there is only one AHB master on a layer.


Memory organization where the least significant byte of a word is at the highest address and the most significant byte is at the lowest address in the word.

See Also Little-endian.


A user-defined point where execution stops so that a debugger can examine the state of memory and registers.

See Also Hardware breakpoint and Software breakpoint.

Cache cleaning

The process of writing dirty data in a cache to main memory.

See Also Dirty data.

Complex Programmable Logic Device (CPLD)

A collection of PAL-type devices in a single package.


An additional processor that is used for certain operations, for example, for floating-point math calculations, signal processing, or memory management.

Core Module

In the context of Integrator, an add-on development board that contains an ARM processor and local memory. Core modules can run standalone, or can be stacked onto Integrator motherboards.

See Also Integrator.


Debug and real-time trace. The infrastructure for monitoring, tracing and debugging a complete system-on-chip.


See Complex Programmable Logic Device.


See Program Status Register.


Central Processor Unit.

Current Program Status Register (CPSR)

See Program Status Register.


See Debug Access Port.

Data breakpoint

A location in the image that is monitored. If the value stored there is accessed in a specific way, the debugger halts execution of the image.

See Also Instruction breakpoint.


Data cache.

Debug Access Port (DAP)

A TAP block that acts as an AMBA (AHB or AHB-Lite) master for access to a system bus. The DAP is the term used to encompass a set of modular blocks that support system-wide debug. The DAP is a modular component, intended to be extendable to support optional access to multiple systems such as memory-mapped AHB and CoreSight APB through a single debug interface.


An application that monitors and controls the execution of a second application. It is usually used to find errors in the application program flow.

Dirty data

When referring to a processor data cache, data that has been written to the cache but has not been written to main memory. Only write-back caches can have dirty data, because a write-through cache writes data to the cache and to main memory simultaneously. The process of writing dirty data to main memory is called cache cleaning.

See Also Cache cleaning.


See Dynamic Linked Library.

Double word

A 64-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.

Dynamic Linked Library

A collection of programs, any of which can be called when required by an executing program. A small program that helps a larger program communicate with a device, such as a printer or keyboard, is often packaged as a DLL.

EmbeddedICE logic

The EmbeddedICE logic is an on-chip logic block that provides TAP-based debug support for ARM processor cores. It is accessed through the TAP controller on the ARM core using the JTAG interface.

See Also IEEE1149.1-2001 and In-Circuit Emulator.

Embedded Trace Buffer (ETB)

The Embedded Trace Buffer provides logic inside the core that extends the information capture functionality of the Embedded Trace Macrocell.

Embedded Trace Macrocell (ETM)

The Embedded Trace Macrocell is the logic inside the core that communicates details of program execution to the external trace port.

Endpoint connection

A debug target processor, normally accessed through an access-provider connection.


The actual hardware and operating system that an application runs on.


See Embedded Trace Buffer.


See Embedded Trace Macrocell.

Flash memory

Nonvolatile memory that is often used to hold application code.


A 16-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.

Hardware breakpoint

A breakpoint that is implemented using non-intrusive additional hardware. Hardware breakpoints are the only method of halting execution when the location is in Read Only Memory (ROM). Using a hardware breakpoint often results in the processor halting completely. This is usually undesirable for a real-time system.

See Also Breakpoint and Software breakpoint.


A computer that provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.


Integrated Circuit.


Instruction cache.



IEEE 1149.1-2001

The IEEE Standard that defines TAP. Commonly, but incorrectly, referred to as JTAG.

See Also Test Access Port.


An executable file that has been loaded onto a processor for execution.

In-circuit Emulator

A device enabling access to and modification of the signals of a circuit while that circuit is operating.

Instruction breakpoint

A location in the image that is monitored. If execution reaches this location, the debugger halts execution of the image.

See Also Data breakpoint.

Instruction Register (IR)

When referring to a TAP controller, a register that controls the operation of the TAP.


A range of ARM hardware development platforms. Core Modules are available that contain the processor and local memory.


See Instruction Register.

Joint Test Action Group (JTAG)

An IEEE group focussed on silicon chip testing methods. Many debug and programming tools use a Joint Test Action Group (JTAG) interface port to communicate with processors. For more information, see IEEE Standard, Test Access Port and Boundary Scan Architecture specification 1149.1-2001 (JTAG).


See Joint Test Action Group.


Memory organization where the least significant byte of a word is at the lowest address and the most significant byte is at the highest address of the word.

See Also Big-endian.


Large Scale Integration.


Low Voltage Differential Signaling.

Memory Management Unit (MMU)

Hardware that controls caches and access permissions to blocks of memory, and translates virtual to physical addresses.


See Memory Management Unit.


Multi-Processor Unit.


A JTAG-based tool for debugging embedded systems.


Abbreviation of System Reset. The electronic signal that causes the target system other than the TAP controller to be reset. This signal is known as nSYSRST in some other manuals.

See Also nTRST.


Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be reset. This signal is known as nICERST in some other manuals.

See Also nSRST.

Open collector

A signal that can be actively driven LOW by one or more drivers, and is otherwise passively pulled HIGH. Also known as a ‘wired AND’ signal.


Printed Circuit Board

Processor core

The part of a microprocessor that reads instructions from memory and executes them, including the instruction fetch unit, arithmetic and logic unit and the register bank. It excludes optional coprocessors, caches, and the memory management unit.

Processor Status Register

See Program Status Register.

Program image

See Image.

Program Status Register (PSR)

Contains information about the current execution context. It is also referred to as the Current PSR (CPSR), to emphasize the distinction between it and the Saved PSR (SPSR), that records information about an alternate processor mode.


See Program Status Register.

RealView Compilation Tools

A suite of tools, together with supporting documentation and examples, that enables you to write and build applications for the ARM family of RISC processors.

RealView Debugger

The latest debugger software from ARM that enables you to make use of a debug agent to examine and control the execution of software running on a debug target. RealView Debugger is supplied in Windows and Linux versions.

RealView ICE

RealView EmbeddedICE interface.

RealView Trace

Provides tracing functionality for RealView ICE.


Changing the address of physical memory or devices after the application has started executing. This is typically done to enable RAM to replace ROM when the initialization has been done.


Returned TCK. The signal that enables Adaptive Clocking.


Real Time Operating System.

Saved Program Status Register (SPSR)

See Program Status Register.

Scan chain

A scan chain is made up of serially-connected devices that implement boundary-scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain. Processors might contain several shift registers to enable you to access selected parts of the device.


A mechanism where I/O requests made in the application code are communicated to the host system, rather than being executed on the target.

Serial Wire Debug (SWD)

Serial Wire Debug is a two-pin, bi-directional, data signal plus clock that replaces the 5-pin or 6-pin JTAG interface. The Serial Wire/JTAG debug port provides access to system memory peripherals and debug configuration registers.

Software breakpoint

A breakpoint that is implemented by replacing an instruction in memory with one that causes the processor to take exceptional action. Because instruction memory must be altered software breakpoints cannot be used where instructions are stored in read-only memory. Using software breakpoints can enable interrupt processing to continue during the breakpoint, making them more suitable for use in real-time systems.

See Also Breakpoint and Hardware breakpoint.


See Program Status Register.

Supervisor Call (SVC)

An instruction that interrupts the program being executed, and passes control to the supervisor.


See Supervisor Call.


See Serial Wire Debug.

Synchronous starting

Setting several processors to a particular program location and state, and starting them together.

Synchronous stopping

Stopping several processors in such a way that they stop executing at the same instant.


See Test Access Port.

TAP Controller

Logic on a device that enables access to some or all of that device for test purposes. The circuit functionality is defined in IEEE1149.1-2001.

See Also Test Access Port and IEEE1149.1-2001.


The target hardware, including processor, memory, and peripherals, real or simulated, on which the target application is running.


The electronic clock signal that times data on the TAP data lines TMS, TDI, and TDO.


The electronic signal input to a TAP controller from the data source (upstream). Usually this is seen connecting the RealView ICE run control unit to the first TAP controller.


The electronic signal output from a TAP controller to the data sink (downstream). Usually this is seen connecting the last TAP controller to the RealView ICE run control unit.

Test Access Port (TAP)

The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is nTRST. This signal is mandatory in ARM cores because it is used to reset the debug logic.


Test Mode Select.


See Trace Port Analyzer.

Trace funnel

A device that combines multiple trace sources onto a single bus.

Trace Port Analyzer (TPA)

A logic analyzer that can capture the details of program execution in real time. RealView Trace is the ARM trace port analyzer.

Trace Port Interface Unit (TPIU)

A trace sink used to drain trace data, and acts as a bridge between the on-chip trace data and the data stream captured by a TPA.


Transistor-transistor logic. A type of logic design in which two bipolar transistors drive the logic output to one or zero. LSI and VLSI logic often used TTL with HIGH logic level approaching +5V and LOW approaching 0V.


Very Large Scale Integration.


A 32-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.

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