5.3.3. Processor exceptions

Some processors provide dedicated hardware to enter debug state when a predetermined event occurs. Available processor events are displayed in the Processor Exceptions List Selection dialog box. See the chapter that describes breakpoints in the RealView Debugger User Guide for more information on this dialog box.

Most ARM cores provide hardware to enter debug state when an exception occurs. This is called vector catch. Some ARM cores, such as ARM7, do not provide vector catch hardware. For these cores, RealView ICE simulates vector catch using instruction breakpoints.

Note

If the exception vectors are in ROM, RealView ICE must use hardware breakpoints to simulate vector catch. This reduces the number of resources available for other purposes.

If RealView ICE uses an instruction breakpoint to simulate reset vector catch, the breakpoint might not be hit when a reset occurs. This is because most systems remap flash or ROM at the exception vectors during reset, and this displaces any instruction breakpoint that might be set. The following warning is output to the RealView Debugger console if RealView ICE simulates reset vector catch using an instruction breakpoint:

Warning: A software breakpoint is being used to simulate reset vector catch.
This may fail to be hit if the memory is remapped when a reset occurs.

The exact behavior of the ARM vector catch hardware depends on the core. ARM9 and ARM10 processors enter debug state only when the specified exception occurs. Other processors such as ARM11 enter debug state whenever the instruction at the exception vector is executed, regardless of whether the exception occurs or not.

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