5.4. Cached data

When debugging a cached processor, RealView ICE uses the strategies now described.

  1. On debug entry.

    • RVI forces Write-Through (WT) on cores that support this debug feature.

    • RVI disables cache line fill on cores that support disabling of this feature in debug.

    • RVI disables Translation Look-aside Buffer (TLB) loads on cores that support disabling of this feature in debug.

    • If data is read from cacheable memory, it is only read into the caches if, and only if, disable linefill is not possible.

    • TLB matches and caches remain enabled.

  2. On data write.

    • If WT is possible, nothing cache-related is performed.

    • If WT is not possible, strategy is core size- and data size-dependent:

    1. RVI can write to memory with caches enabled, and then write disabled, effectively simulating write through.

    2. RVI can clean and invalidate the Dcache and disable it. (The 940T requires that Code Sequences are enabled to do this.)

  3. On restart into debug.

    • On cores that support the features, forced WT is removed, linefills are re-enabled, and TLB loads are enabled. If, and only if, data has been written, the Icache is invalidated. If, and only if, Dcache has been disabled, then it is re-enabled.

    Data writes that could cause the cache operations described include user accesses using RealView Debugger, downloads, and any software breakpoints present in the system.

Note

For the ARM940T core you must configure the Code Sequence... settings in the Debug tab before attempting to debug with the cache(s) enabled. For more specific information on target connection using RealView Debugger, see the RealView Debugger Target Configuration Guide.

When the cache is enabled, the speed of semihosting decreases.

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