1.3.1. Debug extensions to the ARM core

The debug extensions consist of several scan chains around the processor core, and some additional signals that are used to control the behavior of the core for debug purposes. The most significant of these additional signals are:


This core signal enables external hardware to halt processor execution for debug purposes. When HIGH during an instruction fetch, the instruction is tagged as breakpointed, and the core stops if this instruction reaches the execute stage of the pipeline.


This core signal is a level-sensitive input that causes the CPU core to enter debug state when the current instruction has completed.


This core signal is an output from the CPU core that goes HIGH when the core is in debug state so that external devices can determine the current state of the core.

RealView ICE uses these, and other signals, through the debug interface of the processor core, for example by writing to the control register of the EmbeddedICE logic. For more details, see the section that describes the debug interface support of the ARM datasheet or technical reference manual for your core (for example, the ARM7TDMI (Rev 4) Technical Reference Manual).

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