4.6.3. Cortex-R4 FPGA

Figure 4.31 shows the CoreSight topology diagram for Cortex-R4 FPGA.

Figure 4.31. CoreSight system topology diagram - Cortex-R4 FPGA


The Association file for this is:

Name=ARMCS-DP;Type=ARMCS-DP;Name=Cortex-R4;Type=Cortex-R4;ETM=ETMR4;Name=ETMR4;Type=CSETM;TraceOutput0=TPIU;TraceOutput1=ETB;Core=Cortex-R4;Name=ETB;Type=CSETB;Port0=ETMR4;Name=TPIU;Type=CSTPIU;Port0=ETMR4;

The Association file’s content is now described.

Name=ARMCS-DP;Type=ARMCS-DP;

This line specifies the first device in our list is the ARM CoreSight Debug port. Any CoreSight components that are connected using the Debug Port associated with this template must follow this device.

Name=Cortex-R4;Type=Cortex-R4;ETM=ETMR4;

This line specifies that a Cortex-R4 core is connected using the preceding ARMCS-DP. The ETM=ETMR4 section states that the core has an associated ETM called “ETMR4”.

Name=ETMR4;Type=CSETM;TraceOutput0=TPIU;TraceOutput1=ETB;Core=Cortex-R4;

This line specifies that an ETM is accesible using the preceding ARMCS-DP.

TraceOutput0=TPIU signifies that this ETM can output into the component named “TPIU”.

TraceOutput1=ETB signifies that this ETM can output into the component named “ETB”.

Core=Cortex-R4 signifies that the source for trace captured by this ETM is the Cortex-R4 device.

Name=ETB;Type=CSETB;Port0=ETMR4;

This line specifies that a CoreSight ETB is accessible using the preceding ARMCS-DP.

Port0=ETMR4; indicates that the source of trace that is stored in this ETB is the component named “ETMR4”.

Name=TPIU;Type=CSTPIU;Port0=ETMR4;

This line specifies that a CoreSight TPIU is accessible using the preceding ARMCS_DP.

Port0=ETMR4; indicates that the source of trace that is routed through this TPIU is the component named “ETMR4”.

Figure 4.32 shows the Cortex-R4 FPGA Associations.

Figure 4.32. Cortex-R4 FPGA Associations


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