5.4.1. Debugging cores with caches enabled

When debugging a core with caches enabled, you might have to provide the address of an area of memory on the target that can be used exclusively by RealView ICE. On some targets, the RealView ICE software downloads code sequences to this area to perform various tasks, such as cleaning the cache, and accessing the CP15 registers. RealView ICE does not preserve the contents of this area.

A code sequence area is only required for certain cores where the required operations cannot be performed directly over JTAG. If RealView ICE requires a code sequence area, and one has not been enabled, errors are displayed within the debugger. For example:

Error V28305 (Vehicle):Memory operation failed
Warning:Code sequence memory area error
Unable to load code sequence into defined memory area

Note

The code sequence area must be 128 bytes long and in a non-cacheable, readable and writeable area.

To set up a code sequence area, you can use the Debug pane of the Register Window in RealView Debugger or through the options for each specific core in RVConfig. Both mechanisms provide access to per core configuration items for enabling code sequences, and setting the address and size of the code sequence areas. Any settings modified using the Register window in RealView Debugger are ONLY modified for the life of the debug session. Any settings modified using RVConfig are persistent until modified again.

Copyright © 2002, 2004-2008 ARM Limited. All rights reserved.ARM DUI 0155J
Non-Confidential