A.1. Address map and interrupts

Most of the peripheral interrupts are routed direct to the primary interrupt controller (PIC). The Integrator/AP and IM-PD1 combination uses two interrupt controllers, the Integrator/AP (IC) and the IM-PD1 (VIC). Therefore the format of the interrupt handler will have to be modified to reflect the Integrator/CP layout. See the core module documentation for details on enabling, detecting and clearing interrupts.

Table A.1 shows the relationship between interrupts and peripheral addresses.

Table A.1. Peripheral and address map

PeripheralCP module addressCP module IRQAP addressIM-PD1 addressIRQNotes
UART00x16000000PIC 10x16000000-IC 1PL011
UART10x17000000PIC 20x17000000-IC 2PL011
MMCI0x1C000000PIC 23/24-0xC0700000VIC 7/8-
KYBD0x18000000PIC 30x18000000-IC 3-
MOUSE0x19000000PIC 40x19000000-IC 4-
AACI0x1D000000PIC 25-0xC0800000VIC 9-
TSCI0x1E000000PIC 28-0xC0300000VIC 3Not Equivalent
CLCD0xC0000000PIC 22-0xC1000000VIC 11-
GPIO0xC9000000--0xC0400000VIC 4Not Equivalent
Timers0x13000000PIC 5/6/70x13000000-IC 5/6/71MHz ADK timers
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