Integrator®/CP User Guide 4.4.2. Touchscreen controller interface registers

4.4.2. Touchscreen controller interface registers

The mapping of the TSCI registers is shown in Table 4.7.

Table 4.7. Touchscreen controller registers

Address	Name	Type	Function
`0x1E000000`	TS_CTRL	Read/write	Control register
`0x1E000004`	TS_DATA	Read	X Y data register
`0x1E000004`	TS_DATA	Write	Write any value to acknowledge and clear the latched pendown interrupt

The interface consists of an 8-bit control register (write-only) and a 16-bit data read register (read-only). When a value is written to the control register, the controller starts a 24-bit transfer sequence:

The first eight clocks write the control register value to the TSCI.
Busy requires one clock.
The next 12 clocks read data from the TSCI into the data register [11:0].
The remaining three clocks complete the transfer.

The register bit mapping is shown in the tables below.

Table 4.8. TS_CTRL control register

Bit	Name	Function
7	S	Start bit and TSC/CS set low until after X2 read
6:4	A[2:0]	Enable Y (001) or X (101) plates for reading
3	MD	8/12 bit mode (always high, 12-bit resolution)
2	S/D	Single/Differential reference (always low, differential)
1:0	PD[1:0]	Power Down, use 11 for all readings except for last X reading that is 00.

Table 4.9. TS_DATA control register

Bit	Name	Function
15	RDY	The ready status bit indicates that the TSCI has completed processing of the last control value and is ready for a new value. While RDY is low, DATA[11:0] is invalid and the control byte must not be written.
14	PD	The controller PENIRQ generates an IRQ when the pen is down. The interrupt must not be cleared until the end of a complete pen reading sequence (the IRQ line is asserted several times by the reading process). At the end of each reading, PD is checked to see if the pen has been lifted. If so, the PENIRQ can be cleared ready for the next pen down event.
13:12	-	Not used
11:0	DATA[11:0]	Data indicating the X or Y position.

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