4.3.2. LCD power control

Figure 4.4 shows the three Integrator/CP power outputs for the attached display:

Figure 4.4. LCD power supply control

LCD1_BIAS is a variable supply controlled by the MAX686 (U6, DAC-controlled boost/Inverter LCD bias supply) and switched ON and OFF by the MOSFET switch (U26). LCD1_BIAS is varied between 11.5V and 24V in 64 steps using the inputs on pins B9 and B17 on the HDRA socket. These are edge-triggered inputs. The MAX686 is reset to the midpoint by a power-on reset. The MOSFET switch is controlled by the input from B1. The bias control signals are enabled when B30 is LOW and disabled when B30 is HIGH.

LCD0_3V3 and LCD1_3V3 are fixed-level power outputs that are controlled by MOSFET switches within U27. The switches are controlled by the signal on the pin B31 of the HDRA connector.

The power-control signal B31 is controlled by bit 11 in the LCD PrimeCell register LCD_CTRL.

The LCD bias controls are disabled when the VGA display interface is in 24-bit mode, when n24BITEN is LOW. n24BITEN must be HIGH in order to adjust the LCD bias controls.

The signals from the HDRA connector in Figure 4.4 are controlled by the CM_CTRL register in the system controller FPGA:

B1

Bit 9 is LCDBIASUP

B9

Bit 10 is LCDBIASDN

B17

Bit 8 is LCDBIASEN

B30

Bit 19 is n24BITEN.

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