3.6.3. Debug communications interrupts

The processor core incorporates EmbeddedICE hardware. This provides debug communications data read and write registers that are used to pass data between the processor and JTAG equipment. The processor accesses these registers as normal 32-bit read/write coprocessor registers and the JTAG equipment reads and writes the same registers using the relevant scan chain. For a description of the debug communications channel, see the Technical Reference Manual for your core.

You can use interrupts to signal when the debugger writes data into the read data register or reads from the write data register. These interrupts are supported by the CIC within the core module FPGA and can be enabled and cleared by accessing the interrupt registers.

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