3.2.2. Bus connectors HDRA and HDRB

The system bus is connected between the baseboard, core module card, and additional logic modules using the HDRA and HDRB connectors.

Caution

The Integrator/CP supports only one ARM Integrator core module.

Custom core modules can be added, but they must operate in slave mode and communicate with an ARM core module using shared memory.

The signals carried by these connectors are described in Table 3.1 and the pinouts for the base board and core module are shown in Appendix B Connector Pinouts.

Table 3.1. System bus connector signal assignments for AHB-Lite

ConnectorPinsFunction
HDRA

A[31:0]

This is the AHB address bus.

B[31:0]

These carry the display interface signals.

C[31:0]

These carry AHB bus control signals and various interface signals.

D[31:0]

This is the AHB data bus. This uses a bidirectional bus HDATA rather than the separate unidirectional buses HWDATA and HRDATA described in the AMBA specification.
HDRB

E[31:0]

This bus carries the system bus control signals. These are mainly the signals associated with the Integrator system, such as interrupt requests and clocks.There are no arbitration signal connections on the baseboard.

The clock signals, interrupt signals, module ID, and module presence signals are routed so that they rotate up through the stack (see Module-assigned signals).

These pins correspond with the pins labeled H[31:0] on logic modules.

F[31:0]

This set of pins is used to implement a variety of interface connections.

G[16:0]

This set of pins is used to implement the Multi-ICE/JTAG signals and FPGA configuration control signals.

These pins correspond with the J[16:0] pins on logic modules.

Note

There are no free pins. Expansion must use the EXPIM connector on a logic module.

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