3.2.1. AHB-Lite bus protocol

The main system bus uses the AHB-Lite protocol. This is a version of the AHB system bus aimed at single-master system designs. The ARM core is the only master permitted. The system bus allows the processor to access resources on the baseboard and on other modules.

The AHB-Lite implementation on the Integrator/CP has the following main features:

The core module is an AHB-Lite master and has a similar signal interface to a full AHB master but differs as follows:

The LOCK signal is tied to ground on the Integrator/CP. Lock is normally used to indicate to a slave that no other transfer can occur while the core requires the locked access. For the Integrator/CP however, there is only one core module present.

Because a number of signal paths are registered, the bridge interface can insert BUSY wait states during a transfer. The burst-read transaction takes a minimum of 2 clock cycles (data with at least one wait state per unit transfer). For the burst-write transaction, the number of clock cycles depends upon whether the transfer can be buffered. Non-buffered writes take a minimum of 3 clock cycles (data and at least two inserted wait states per unit transfer). Buffered writes complete in a single cycle when the pipeline is filled

Note

Table B.1 provides a full listing of the external system bus signals. More details on the AHB bus can be found on the ARM website at www.arm.com\arm\amba.

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