3.7. Clocks

Table 3.9 provides a summary of the clock signals on the CP baseboard.

Table 3.9. Clock signal descriptions

Signal name Description
UARTCLKThis is a fixed-frequency 14.7456MHz clock generated by IC525 on the baseboard from a 25MHz crystal. It is supplied to the UARTs within the system controller FPGA to provide a 16x baud-rate clock, allowing baud rates of up to 460,800 to be selected in the UART registers. Although the UART is capable of baud rates up to 460kbps, the line drivers on the board are only guaranteed to operate to 120kbps
AACI_BIT_CLKThis is a fixed-frequency 12.288MHz clock generated by the audio CODEC from a 24.576MHz crystal on the baseboard. It also provides a reference clock for the AACI within the FPGA.
SYSCLKThis is the system bus clock. This clock has the same phase and frequency as the processor bus clock.
MCI_5This clock signal is supplied by the MMCI in the system controller FPGA to the MMC socket on the baseboard. See MMC interface.

The clock architecture varies for each CP and core module combination (see the documentation for your core module for details).

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