3.6.2. Secondary interrupt controller

The SIC is implemented in the CP baseboard PLD and combines interrupts from MMC socket, the UART ring indicator bits, installed logic modules, and a software generated interrupt to the CPPLDINT input of the PIC.

The MMC interrupt on the SIC is generated by the card insertion detect switch and is different from the MMCI interrupts in the PIC generated by the MMCI PrimeCell. See MMC interface.

The secondary controller provides a set of registers to control and handle interrupts. The secondary interrupt control registers are listed in Table 3.7.

Table 3.7. Secondary interrupt register addresses

Address

Name

Type

Size

Function

0xCA000000

SIC_INT_STATUS

Read

22

SIC gated interrupt status

0xCA000004

SIC_INT_RAWSTAT

Read

22

SIC raw interrupt status

0xCA000008

SIC_INT_ENABLESET

Read/write

22

SIC enable set

0xCA00000C

SIC_INT_ENABLECLR

Write

22

SIC enable clear

0xCA000010

SIC_INT_SOFTSET

Read/write

16

Software interrupt set

0xCA000014

SIC_INT_SOFTCLR

Write

16

Software interrupt clear

The secondary interrupt controller bits are described in Table 3.8.

Table 3.8. Secondary interrupt register bit assignments

Bit

Name

Function

[31:12]-Reserved
[11:4]LM_INT[7:0]Interrupt sources from logic modules
[3]CARDINMultimedia card insertion interrupt
[2]RI1UART1 ring indicator interrupt
[1]RI0UART0 ring indicator interrupt
[0]SOFTINT

Software interrupt

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