4.3.4. VGA display interface

The Integrator/CP provides a VGA display interface implemented with a THS8134A triple DAC as shown in Figure 4.5. The video DAC can be configured for 24-bit (3x8 bit) or 16-bit RGB operation. The blanking and synchronization input signals are tied high to 3.3V. Pixel data and the horizontal and vertical synchronization signals are supplied by the display interface within the FPGA on the core module.

The 24-bit and 16-bit modes do not use the color palette. In 24-bit mode, color information is organized 8-8-8 bits. In 16-bit mode, there is 1 bit for intensity, then 5-5-5 bits for color.

Figure 4.5. VGA interface architecture

The signal n24BITENABLE on B30 is used to enable the lower two bits on each of the three color channels. These are enabled when n24BITENABLE is LOW and disabled when n24BITENABLE is HIGH.

The timing for VGA and SVGA outputs are shown in Table 4.3.

Table 4.3. VGA and SVGA timing

WaveformPartVGA (640x480)SVGA (800x600)
One lineFront porch31 pixels19 pixels
Horizontal sync.63 pixels164 pixels
Back porch63 pixels19 pixels
Video640 pixels800 pixels
One fieldFront porch11 lines5 lines
Vertical sync.24 lines61 lines
Back porch8 lines5 lines
Video480 lines600 lines
Aux. ClockFrequency25MHz.36MHz
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