3.6. Interrupt controllers

There are three interrupt controllers for the Integrator/CP system:

See the manual for your core module for more details of the primary and debug communications interrupt controllers. The secondary controller on the baseboard provides a set of registers to control and handle peripheral interrupts.

Figure 3.6 shows the interrupt control architecture for the Integrator/CP system.

Figure 3.6. Interrupt architecture

The IRQ and FIQ controllers each provide three registers for controlling and handling interrupts. These are:

The way that the interrupt enable, clear, and status bits function for each interrupt is illustrated in Figure 3.7 and described in the following sections and the core module documentation. The illustration shows the control for one IRQ bit. The remaining IRQ bits and FIQ bits are controlled in a similar way.

Figure 3.7. Interrupt control

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