3.6.5. Interrupt routing between Integrator modules

Figure 3.8 shows how the IRQ signals are routed from the logic modules down to the interrupt controllers. It highlights how the signals are routed so that, for example, the interrupt request from logic module 2 connects to LM_INT2 (IRQ[2]) on the baseboard. The same rerouting applies for logic module 1 and 3. The operation of the interrupts relies on the core module being mounted on the baseboard first with the logic modules on top.

To simplify the description, this document refers to the logic modules source interrupts to the SIC as LM_INT[7:0]. The other signal names used in this diagram are those that appear on the schematic diagrams for the different modules. The signal names are not relevant to the final destination (IRQ or FIQ) of the signal in the ARM core.

For maximum flexibility, you can connect the eight logic module interrupt lines (LM_INT[7:0]) to the logic module interrupts as appropriate sources for your system. The SIC allows any of the interrupt sources LM_INT[7:0] to activate the CPPLDINT input on the PIC.

Because the signals route through the SIC, determining the source of an interrupt might require interrogating first the primary and then the secondary controller. The time required for the extra instructions might cause a problem with interrupt latency in some situations. To improve latency, FIQ[0] and IRQ[0] (as LM_LLINT[1:0]) are also routed to the PIC as well.

Note

Ensure that the correct interrupt line is driven. See the routing pattern in Figure 3.8.

Although the signal rotation scheme is identical, the logic module interrupt routing scheme used on the Integrator/CP is not the same as that used on the Integrator/AP. In an Integrator/AP system, the nFIQ[3:0] pins on a logic module are unused and each logic module typically outputs only one interrupt source on its nIRQ[0] line.

Modules produced for the Integrator/AP should work on the Integrator/CP without the need to re-assign the interrupt signal positions. Logic modules in positions 1, 2, and 3 appear on the Integrator/CP interrupt lines LM_INT[1] to LM_INT[3] and lines LM_INT[7:4] are not connected.

Figure 3.8. Interrupt signal routing

Copyright © 2002 ARM Limited. All rights reserved.ARM DUI 0159B
Non-Confidential