4.3.1. LCD interfaces

Figure 4.3 shows the architecture of the CLD display interface and shows the signals used to provide pixel data and for buffer control.

Figure 4.3. LCD interfaces

B27 is used to enable the signals on J13 (LCD1_xxx), and B28 is used to enable the buffers for the Sharp display signals on J14 (LCD0_xxx). The enable LCD1 and enable LCD0 control bits are located in the CM_CTRL register at 0x1000000C. See the manual for your core module for more details.

If you have a PrimeCell license and the HDL source, you can define the assignment of the generic LCD display interface signals to suit your particular application. However, Figure 4.3 shows the default functional assignment.

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