3.6.1. Primary interrupt controller

The PIC is implemented within the system controller FPGA on the core module and handles the majority of interrupts from the system. A substantial number of interrupts are reserved, maintaining compatibility with other modules within the Integrator family.

There are separate controllers for IRQ and FIQ, allowing any interrupt source to be assigned to either. The PIC provides a set of registers to control and handle interrupts.

The Integrator/CP provides interrupt controllers for both IRQs and FIQs that maintain compatibility with other Integrator modules to ensure code portability. There are, however, some subtle differences (see Appendix A Porting Integrator/AP and IM-PD1).

An example of the primary interrupt control registers is provided in Table 3.5. The bit assignment for interrupts in the status, raw status, and enable registers for the IRQ and FIQ interrupt controllers is similar and is shown in Table 3.6.

Note

Refer to the documentation supplied with your core module for more information on the primary interrupt controller and registers.

Table 3.5. Example of primary interrupt register addresses

Address

Name

Type

Size

Function

0x14000000

PIC_IRQ_STATUS

Read

22

IRQ gated interrupt status

0x14000004

PIC_IRQ_RAWSTAT

Read

22

IRQ raw interrupt status

0x14000008

PIC_IRQ_ENABLESET

Read/write

22

IRQ enable set

0x1400000C

PIC_IRQ_ENABLECLR

Write

22

IRQ enable clear

0x14000010

PIC_INT_SOFTSET

Read/write

16

Software interrupt set

0x14000014

PIC_INT_SOFTCLR

Write

16

Software interrupt clear

0x14000020

PIC_FIQ_STATUS

Read

22

FIQ gated interrupt status

0x14000024

PIC_FIQ_RAWSTAT

Read

22

FIQ raw interrupt status

0x14000028

PIC_FIQ_ENABLESET

Read/write

22

FIQ enable set

0x1400002C

PIC_FIQ_ENABLECLR

Write-only

22

FIQ enable clear

Table 3.6. Primary interrupt register bit assignments

Bit

Name

Function

[31:29]-Reserved
[28]TS_PENINTTouchscreen pen-down event interrupt
[27]ETH_INTEthernet interface interrupt
[26]CPPLDINTInterrupt from secondary interrupt controller, see Secondary interrupt controller.
[25]AACIINTAudio interface interrupt
[24]MMCIINT1MultiMedia card interface
[23]MMCIINT0MultiMedia card interface

[22]

CLCDCINT

Display controller interrupt

[21:11]

-Reserved

[10]

LM_LLINT1

Logic module low-latency interrupt 1

[9]

LM_LLINT0

Logic module low-latency interrupt 0

[8]

RTCINT

Real time clock interrupt

[7]

TIMERINT2

Counter-timer 2 interrupt

[6]

TIMERINT1

Counter-timer 1 interrupt

[5]

TIMERINT0

Counter-timer 0 interrupt

[4]

MOUSEINT

Mouse interrupt

[3]

KBDINT

Keyboard interrupt

[2]

UARTINT1

UART 1 interrupt

[1]

UARTINT0

UART 0 interrupt

[0]

SOFTINT

Software interrupt

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