3.4.2. Core module system controller FPGA

The system controller FPGA for the Integrator/CP is located on the core module. It contains the main bus bridges, memory controllers, and peripheral controllers.

Note

The core module FPGA must have an appropriate Integrator/CP-compatible image in order to control the peripherals on the Integrator/CP baseboard.

FPGA image selection

You can use Multi-ICE to reprogram the PLD, FPGA, and flash when the system is placed in configuration mode.

The configuration flash on the core module can store up to four images for the system controller FPGA. The images are selected by the CFGSEL[1:0] signals from the baseboard as shown in Table 3.2. For the Integrator/CP, the CP-AHB-Lite image is used.

Table 3.2. Image selection

CFGSEL[1]CFGSEL[0]Image
00ASB
01Reserved
10AHB
11CP-AHB-Lite

Note

The Integrator/CP drives the CFGSEL[1:0] signals high. The values for CFGSEL[1:0] are preprogrammed into the baseboard PLD.

For more details on image selection, see the documentation supplied with your core module.

Peripheral bus

Figure 3.3 shows the APB peripherals. These are implemented using PrimeCell or ADK devices synthesized into the FPGA on the core module.

Figure 3.3. APB peripherals

The APB is an AMBA-compliant bus optimized for minimum power and reduced interface complexity. It is used to interface peripherals, such as the UARTs and the Keyboard and Mouse Interface (KMI), that do not require the high performance of the AHB.

The AHB-APB bridge is an AHB slave that provides an interface between the high- speed AHB domain and the low-power APB domain. Because the APB is not pipelined, wait states are added during transfers to and from the APB when the AHB is required to wait for the APB protocol.

Copyright © 2002 ARM Limited. All rights reserved.ARM DUI 0159B
Non-Confidential