3.3. Module-assigned signals

A number of signals are routed between the HDRA and HDRB plug and socket on the core module and logic modules so that they rotate up through the stack. The signal rotation allows interrupt and memory control based on the cards position in the stack without the requirement for changing jumpers on a board if its position in the stack is changed.

The signals that are rotated are:

nIRQ[3:0]

These are the interrupt request signals from the logic modules. They are described in Interrupt controllers.

nFIQ[3:0]

These are the interrupt request signals from the logic modules. They are described in Interrupt controllers.

nPPRES[3:0]

These are the module presence signals from the logic modules. They indicate to the address decoder that a logic module has been added to the system and is responsible for generating bus responses for its own address space (see Register overview). On the logic modules these signals correspond to the nEPRES[3:0] signals. On the Integrator/CP, three logic modules can be added, but only one core module is permitted. See Logic module expansion memory space.

SYSCLK[3:0]

These are the system bus clock signals rotated up through the stack to ensure even distribution and signal loading.

ID[3:0]

The signals rotate up through the stack to indicate the position of a board in the stack of modules. The signals are only used by optional logic modules. Only one core module can be used and must always at the bottom of the stack.

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