4.5.2. PrimeCell AACI functional overview

The ARM PrimeCell Advanced Audio CODEC Interface (AACI) is an AMBA slave block that connects to the APB. The PrimeCell AACI provides communication with the CODEC using the AC-link protocol. This section provides a brief overview of the AACI. For detailed information, see ARM PrimeCell Advanced Audio CODEC Interface (PL041) Technical Reference Manual.

Figure 4.10 shows a simplified block diagram of the PrimeCell AACI.

Figure 4.10. Simplified block diagram of the PrimeCell AACI

The AACI issues commands and audio data to the CODEC using the AACI_SDATA_OUT signal. It receives status and audio data from the CODEC using the AACI_SDATA_IN signal. Data is passed using 256-bit AC-link frames synchronized by AACI_SYNC and contained in two phases:

Tag phase

The tag phase contains slot 0 that provides a 16-bit qualifier for the remaining slots in the frame.

Data phase

The data phase contains 12 slots that provide commands or status and data to or from the audio channels in the CODEC. These slots are 20-bits long.

The start of an audio frame is signaled by the rising edge of AACI_SYNC signal that goes HIGH during the final bit of previous frame and remains HIGH for 16 AACI_BIT_CLK cycles.

The key features of communications using the AC-link are:

The AACI contains an 8-entry x 20-bit (standard) receive FIFO and an 8-entry x 20-bit transmit FIFO in which data phase slots are buffered.

For received data, each bit of a received frame on AACI_SDATA_IN is shifted into the receive shift register on the falling edge of AACI_BIT_CLK. Data is clocked out of the shift register at the end of each slot.

For transmitted data, each bit on AACI_DATA_OUT is clocked into the transmit shift register from the frame generator or slot 0 generator and is shifted out one bit at a time on the rising edge of AACI_BIT_CLK.

The slot 0 generator generates the slot 0 tag information and outputs it to the transmit shift register. The frame generator generates slots 1 to 12 and outputs them to the transmit shift register. (See Figure 4.11.)

The frame decoder qualifies the data of slots 1 to 12 that is output from the receive shift register, depending on data present in slot 0, and outputs it to the receive FIFO channel or slot receive registers.

Figure 4.11. AC97 bidirectional audio frame

When the AC-link is active, the timing controller drives the AACI_SYNC signal based on the AACI_BIT_CLK signal from the off-chip CODEC. When the AC-link is inactive, the timing controller drives the internal register value on the AACI_SYNC.

Individual maskable, active HIGH interrupts are generated by the PrimeCell AACI and a combined interrupt output is also generated as an OR function of the individual interrupt requests.

The PrimeCell AACI uses two clock signals, the APB bus clock PCLK and AACI_BIT_CLK. The frequency of AACI_BIT_CLK is fixed at 12.288MHz.

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